Sony HCD-GTX88 Service Manual page 72

HCD-GTX88
IC401 M30622MEP-A75FPU0 (SYSTEM CONTROL) (MAIN BOARD (1/4))
Pin No. Pin Name
1 XRST
2 MMUTE
3 CD CCE
4 SIRCS
5 CD CLK
6 MP3 IREQ
7 SOURCE SEL1
8 BYTE
9 CNVss
10 XC IN
11 XC OUT
12 RESET
13 X OUT
14 VSS
15 X IN
16 VCC
17 NMI
18 SOURCE SEL2
19 SBSY
20 AC CUT
21 BUS3
22 BUS2
23 BUS1
24 BUS0
25 EFFECTOR S0
26 EFFECTOR S1
27 EFFECTOR S2
28 EFFECTOR SEL
29 IIC CLK
30 IIC DATA
31 USBRST
32 CD POWER
STBY LED/FAN
33
CONTROL
34 USB SERIAL CTS0
35 USB SERIAL TXD0
36 USB SERIAL RXD0
37 GC RESET
38 USB SERIAL RTS0
39 SEL SW
40 USB PWR
41 OPEN SW
42 TBL SENSE
43 E-3
44 E-2
45 E-1
46 TMF
47 TMR
48 LMF
72
I/O
O Reset signal output to the digital signal processor "L":reset
O Control port for the digital signal processor motor driver mute
O Chip enable contor port to the digital signal processor
I Remote control signal input
O Serial date transfer clock signal output to the digital signal processor
I Digital signal decoder request pin to master control
Select function input for effector mode (CD/USB/Video in: "L",
O
Tuner/Tape/Audio in: "H")
— Ground pin
— Ground pin
I Sub system clock input (32.768 kHz)
O Sub system clock output (32.768 kHz)
System reset signal input from the reset signal IC "L": reset After the power
I
supply rises, "L" is input for several hundreds msec and then change to "H".
O Main system clock output (5 MHz)
— Ground pin
I Main system clock input (5 MHz)
— Power supply pin (+3.3 V)
I Non-maskable interrupt input
Select function input for effector mode (CD/USB/Tuner/Tape: "H",
O
Audio in/Video in: "L")
I Subcode sync detection signal input from the digital signal processor
I AC off detection signal input from the reset signal IC "L": AC Cut detected
I/O Data bus line for CD communication with master control
I/O Data bus line for CD communication with master control
I/O Data bus line for CD communication with master control
I/O Data bus line for CD communication with master control
O Effector circuitry delay time selection bit 0 signal output
O Effector circuitry delay time selection bit 1 signal output
O Effector circuitry delay time selection bit 3 signal output
O Effector circuity bypass control signal output "H": bypass
I/O Clock signal for IIC communication between Master controller and Display controller
I/O Data signal for IIC communication between Master controller and Display controller
O Reset signal output to USB control IC "L": reset
O Power on/off control signal output to BU section "H": power on
O LED drive signal output of power indicator and fan on/off control port
I Serial send control signal input from USB IC
O UART serial transmission data line signal output to USB IC
I UART serial reception data line signal output from USB IC
O Reset signal output to display control IC "L": reset
O Serial receive control output from USB IC
O USB and CD control switch CD (H)/USB (L)
O Power on/off control signal output to USB section Power On: H
I Eject detection signal input from the CD mechanism
I Disc tray position detection signal input from the CD mechanism
I Disc tray status detection signal input from the CD mechanism
I Disc tray status detection signal input from the CD mechanism
I Disc tray status detection signal input from the CD mechanism
O CD mechanism turning motor control signal output
O CD mechanism turning motor control signal output
O CD mechanism loading motor control signal output
Pin Description