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Motorola M68CPU32BUG User Manual

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M68CPU32BUG/D
REV 1
May 1995
M68CPU32BUG DEBUG MONITOR
USER'S MANUAL
M68CPU32BUG/D
© MOTOROLA, INC., 1991, 1995; All Rights Reserved

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Summary of Contents for Motorola M68CPU32BUG

  • Page 1 M68CPU32BUG/D REV 1 May 1995 M68CPU32BUG DEBUG MONITOR USER’S MANUAL M68CPU32BUG/D © MOTOROLA, INC., 1991, 1995; All Rights Reserved...
  • Page 2 Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.

  • Page 3: Table Of Contents

    3.2 Block Of Memory Compare (BC) ..................3-3 3.3 Block Of Memory Fill (BF)....................3-5 3.4 Block Of Memory Move (BM)................... 3-7 3.5 Breakpoint Insert/Delete (BR/NOBR)................3-9 3.6 Block Of Memory Search (BS)..................3-10 3.7 Block Of Memory Verify (BV) ..................3-13 M68CPU32BUG/D REV 1...
  • Page 4 4.1.1.1 Machine-Instruction Operation Codes ............4-1 4.1.1.2 Directives......................4-1 4.1.2 M68300 Family Resident Structured Assembler Comparison......... 4-2 4.2 Source Program Coding...................... 4-2 4.2.1 Source Line Format ....................4-3 4.2.1.1 Operation Field....................4-3 4.2.1.2 Operand Field ....................4-4 M68CPU32BUG/D REV 1...
  • Page 5 5.2.18 Compare Two Strings (.STRCMP) ................ 5-22 5.2.19 Timer Initialization (.TM_INI)................5-23 5.2.20 Read Timer (.TM_RD)................... 5-24 5.2.21 Start Timer at T=0 (.TM_STR0) ................5-25 5.2.22 Output String with Data (.WRITD/WRITLN) ............5-27 5.2.23 Output String Using Character Count (.WRITE/WRITELN)........ 5-29 M68CPU32BUG/D REV 1...
  • Page 6 Walk a Bit Test (MT F)..................6-18 6.5.7 Refresh Test (MT G) ....................6-19 6.5.8 Random Byte Test (MT H)..................6-20 6.5.9 Program Test (MT I) ....................6-21 6.5.10 Test and Set Test (MT J) ..................6-22 6.6 Bus Error Test (BERR)..................... 6-23 M68CPU32BUG/D REV 1...
  • Page 7 C.4 Communication Formats ....................C-14 C.5 BCC REV. A Chip Selection Summary ................C-15 C.6 BCC REV. B Chip Selection Summary................C-16 C.7 BCC REV. C Chip Selection Summary ................C-17 C.8 Platform Board (PFB) REV. C Compatibility..............C-18 C.9 CPU32BUG Questions and Answers ................C-19 M68CPU32BUG/D REV 1...
  • Page 8 B-1. Self-Test Error Messages....................B-1 C-1. CPU32Bug Customization Area..................C-5 C-2. MCU SCI Communication Formats .................C-14 C-3. Rev. A Chip Selection Summary..................C-15 C-4. Rev. B Chip Selection Summary ..................C-16 C-5. BCC Rev. C Chip Selection Summary ................C-17 C-6. PFB Rev. C Compatibility....................C-18 M68CPU32BUG/D REV 1...

  • Page 9: Chapter 1 General Information

    (i.e., GO) then control may or may not return to CPU32Bug. This depends upon the user program function. CPU32Bug is similar to Motorola’s other debugging packages, but there are two noticeable differences. Many of the commands are more flexible with enhanced functionality. And the debugger has more detailed error messages and an expanded on-line help facility.

  • Page 10: Cpu32Bug Operation Mode Flow Diagram

    DISPLAY WARM EXECPTION CONFIDENCE TEST START MESSAGE EXCEPTION SET DEBUGGER HANDLERS DIRECTORY SAVE TARGET DISPLAY DEBUGGER NAME & VERSION STATE DISPLAY RESULTS OF CONFIDENCE TEST DISPLAY TARGET REGISTERS GO TO MAIN Figure 1-1. CPU32Bug Operation Mode Flow Diagram M68CPU32BUG/D REV 1...

  • Page 11: Using This Manual

    Use the following set-up procedure to enable CPU32Bug to operate with the BCC: 1. Configure the jumpers on the BCC module. Refer to the EVK User’s Manual Motorola publication number M68332EVK/AD1 or M68331EVK/AD1. 2. Connect the DB-9 serial communication cable connector to the terminal or host computer which is to be the CPU32Bug system console.

  • Page 12: System Restart

    Abort generates a non-maskable, level-seven interrupt. The target registers reflect the machine state at the time of an abort and are displayed on the display screen. Any breakpoints installed in the user code are removed and the breakpoint table remains intact. Control is then returned to the debugger. M68CPU32BUG/D REV 1...

  • Page 13: Break

    The target instruction stack pointer (SSP) is set to the top of the user space. Register initialization is done solely as a convenience for the user. Consult the CPU32 Reference Manual for information regarding actual register values during a power- on/reset. M68CPU32BUG/D REV 1...

  • Page 14: Bcc Memory Map

    RAM, can be configured on power-up/reset by using the Initialization Table (INITTBL) covered in Appendix C. (3) Floating Point Coprocessor - MC68881/MC68882 (4) Platform Board (5) Depends on the memory device type used. Figure 1-2. BCC Memory Map M68CPU32BUG/D REV 1...

  • Page 15: Terminal Input/Output Control

    ’’^S’’ and ’’^Q’’ respectively by CPU32Bug, but may be changed by the user using the PF command. The initialized (default) mode operations are: ^S (wait) Console output is halted. ^Q (resume) Console output is resumed. M68CPU32BUG/D REV 1...
  • Page 16 GENERAL INFORMATION M68CPU32BUG/D REV 1...

  • Page 17: Chapter 2 Debug Monitor Description

    Or after entering a TRACE (T) command, entering a carriage return (<CR>) only traces the next instruction. Multiple debugger commands may be entered on a single command line by separating the commands with the explanation point (!) character. M68CPU32BUG/D REV 1...

  • Page 18: Syntactic Variables

    Count; the same syntax as < EXP> . <RANGE> A range of memory addresses which may be specified either by < ADDR><DEL><ADDR> or by <ADDR> :<COUNT> . <TEXT> An ASCII string of as many as 255 characters, delimited with single quote marks (’TEXT’). M68CPU32BUG/D REV 1...

  • Page 19: Expression As A Parameter

    Evaluation of an expression is always from left to right unless parentheses are used to group part of the expression. There is no operator precedence. Sub-expressions within parentheses are evaluated first. Nested parenthetical sub-expressions are evaluated from the inside out. M68CPU32BUG/D REV 1...

  • Page 20: Address As A Parameter

    MC68300 Family one-line assembler. All control addressing modes are allowed. An address+offset register mode is also allowed. Table 2-1 summarizes the address formats which are acceptable for address parameters in debugger command lines. M68CPU32BUG/D REV 1...

  • Page 21: Offset Registers

    In the event that an address falls in two or more offset register ranges, the one that yields the least offset is chosen. NOTE Relative addresses are limited to 1 megabyte (5 digits), regardless of the range of the closest offset register. M68CPU32BUG/D REV 1...
  • Page 22 00004+R0 4280 CLR.L 00006+R0 1018 MOVE.B (A0)+,D0 00008+R0 5340 SUBQ.W #1,D0 0000A+R0 12D8 MOVE.B (A0)+,(A1)+ 0000C+R0 51C8FFFC D0,$A+R0 00010+R0 4CDF0101 MOVEM.L (A7)+,D0/A0 00014+R0 4E75 CPU32Bug> For Additional information about the offset registers, see the OF command description. M68CPU32BUG/D REV 1...

  • Page 23: Port Numbers

    Avoiding contamination of the debugger operating environment is explained in the following paragraphs. CPU32Bug uses certain MCU on-board resources and may also use off-board system memory to store temporary variables, exception vectors, etc. If the user violates CPU32Bug dependent memory space, then the debugger may not function. M68CPU32BUG/D REV 1...

  • Page 24: Cpu32Bug Vector Table And Workspace

    In this way, the operation of the debugger facility (through an exception) is transparent to the user, but it does change the locations on the stack. M68CPU32BUG/D REV 1...

  • Page 25: Using Cpu32Bug Target Vector Table

    CPU32Bug maintains a separate vector table for its own use in a 1k byte space in the reserved memory space. The debugger vector table is completely transparent to the user and no modifications should ever be made to it. M68CPU32BUG/D REV 1...

  • Page 26: Creating Vector Tables

    The user program must ensure an exception stack frame is in the stack and that it is identical to one the processor would create for the particular exception. It may then jump to the address of the exception handler. M68CPU32BUG/D REV 1 2-10...

  • Page 27: Cpu32Bug Generalized Exception Handler

    Cur. PC=00003000 Cnt. Reg.=0001 =00003000 =A700=TR:ALL_S_7_..VBR =00000000 SFC =5=SD DFC =5=SD USP =0000FC00 SSP* =00003FE8 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00003FE8 00003000 203900F0 0000 MOVE.L ($F00000).L,D0 CPU32Bug> M68CPU32BUG/D REV 1 2-11...

  • Page 28: Function Code Support

    Sets the function code to <FC> value. <ADDR>^^ Toggles the displaying of function code values. <ADDR>^<FC>= Sets the function code to <FC> and the default function code to <FC>. The default value at power up is SD. M68CPU32BUG/D REV 1 2-12...
  • Page 29 SP or UP, depending on the state of the S-bit in the SR. Though function codes are supported, the BCC hardware does not require function codes to operate. EXAMPLE To change data at location $5000 in the user data space. CPU32Bug>m 5000^ud<CR> 00005000^UD 0000 1234.<CR> CPU32Bug> M68CPU32BUG/D REV 1 2-13...
  • Page 30 DEBUG MONITOR DESCRIPTION M68CPU32BUG/D REV 1 2-14...

  • Page 31: Introduction

    3.12 Go To Temporary Breakpoint 3.13 Help 3.14 Load S-Records from Host 3.15 MA/NOMA Macro Define/Display/Delete 3.16 Macro Edit 3.17 MAL/NOMAL Macro Expansion Listing Enable/Disable 3.18 Memory Display 3.19 Memory Modify (alias M) 3.20 Memory Set 3.21 M68CPU32BUG/D REV 1...
  • Page 32 2.1. In the examples of the debugger commands all user inputs are in bold type. This helps clarify examples by distinguishing user input characters from CPU32Bug output characters. The symbol <CR> represents the carriage return key on the user’s terminal keyboard. This symbol indicates the user should enter a carriage return. M68CPU32BUG/D REV 1...

  • Page 33: Block Of Memory Compare (Bc)

    THIS IS A TEST!! 00004110 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ....EXAMPLES CPU32Bug>BC 4000,401F 4100<CR> Effective address: 00004000 Effective address: 0000401F Effective address: 00004100 CPU32Bug> Memory compares, nothing printed M68CPU32BUG/D REV 1...
  • Page 34 Effective address: 00004100 CPU32Bug> Memory compares, nothing printed CPU32Bug>MM 410F;B<CR> 0000410F 21? 0.<CR> CPU32Bug> Create a mismatch CPU32Bug>BC 4000:20 4100;B<CR> Effective address: 00004000 Effective count : &32 Effective address: 00004100 0000400F: 21 0000410F: 00 CPU32Bug> Mismatch is printed out M68CPU32BUG/D REV 1...

  • Page 35: Block Of Memory Fill (Bf)

    4E71 4E71 4E71 4E71 NqNqNqNqNqNqNqNq 00004010 4E71 4E71 4E71 4E71 4E71 4E71 4E71 4E71 NqNqNqNqNqNqNqNq 00004020 0000 0000 0000 0000 0000 0000 0000 0000 ....Since no option was specified, the length of the data field defaulted to word. M68CPU32BUG/D REV 1...

  • Page 36: Block Of Memory Fill Bf

    Effective address: 00004000 Effective count : &24 CPU32Bug>MD 4000:18<CR> 00004000 0000 0001 0002 0003 0004 0005 0006 0007 ....00004010 0008 0009 000A 000B 000C 000D 000E 000F ....00004020 0010 0011 0012 0013 0014 0015 0016 0017 ....M68CPU32BUG/D REV 1...

  • Page 37: Block Of Memory Move (Bm)

    This utility is useful for patching assembly code in memory. Suppose the user had a short program in memory at address $6000. CPU32Bug>MD 6000 600A;DI<CR> 00004000 D480 ADD.L D0,D2 00004002 E2A2 ASR.L D1,D2 00004004 2602 MOVE.L D2,D3 00004006 4E4F0021 SYSCALL .OUTSTR 0000400A 4E71 M68CPU32BUG/D REV 1...
  • Page 38 00006002 E2A2 ASR.L D1,D2 ? NOP<CR> 00006002 4E71 00006004 E2A2 ASR.L D1,D2 ? .<CR> CPU32Bug> CPU32Bug>MD 6000 600C;DI<CR> 00006000 D480 ADD.L D0,D2 00006002 4E71 00006004 E2A2 ASR.L D1,D2 00006006 2602 MOVE.L D2,D3 00006008 4E4F TRAP 0000600C 4E71 CPU32Bug> M68CPU32BUG/D REV 1...

  • Page 39: Breakpoint Insert/Delete (Br/Nobr)

    EXAMPLE Set multiple breakpoints CPU32Bug>BR 4000,4200 4700:&12 <CR> BREAKPOINTS 00004000 00004200 00004700:C Delete one breakpoint CPU32Bug>NOBR 4200 <CR> BREAKPOINTS 00004000 00004700:C Delete all breakpoints CPU32Bug>NOBR <CR> BREAKPOINTS CPU32Bug> M68CPU32BUG/D REV 1...

  • Page 40: Block Of Memory Search (Bs)

    Mode 3 DATA VERIFICATION — If the ''V'' (verify) option is selected and the memory contents do not match the user-specified pattern, then addresses and data are displayed. Otherwise this mode is identical to Mode 2. M68CPU32BUG/D REV 1 3-10...
  • Page 41 Mode 1, using <RANGE> with count Effective address: 00003000 and size option: count is displayed in Effective count : &48 decimal, and address of each occur- 0000300A 0000300C 00003020 00003023 rence of the string is output. M68CPU32BUG/D REV 1 3-11...
  • Page 42 Effective address: 00003000 Effective address: 0000302F 00003002|0045 00003004|7272 00003006|6F72 00003008|2053 0000300A|7461 0000300C|7475 0000300E|733D 00003010|3446 00003012|2F2F 00003014|436F 00003016|6E66 00003018|6967 0000301A|5461 0000301C|626C 0000301E|6553 00003020|7461 00003022|7274 Mode 3, mask option, scan for words with low nibble non-zero: 17 non-matching locations found. M68CPU32BUG/D REV 1 3-12...

  • Page 43: Block Of Memory Verify (Bv)

    Addresses outside of the specified range are not read under any condition. ''Effective address'' messages displayed by the command show the extent of the area read. M68CPU32BUG/D REV 1 3-13...
  • Page 44 00007010 0008 FFFF 000A 000B 000C 000D 000E 000F ....00007020 0010 0011 0012 0013 0014 0015 0016 0017 ....Default size is Word. CPU32Bug>BV 7000:18,0,1 <CR> Effective address: 00007000 Effective count : &24 00007012|FFFF Mismatches are printed out. CPU32Bug> M68CPU32BUG/D REV 1 3-14...

  • Page 45: Data Conversion (Dc)

    The subsequent examples assume A0=00003000 and the following data resides in memory: 00003000 11111111 22222222 33333333 44444444 ..""""3333DDDD CPU32Bug>DC (A0)<CR> 00003000 = $3000 = &12288 CPU32Bug>DC ([A0])<CR> 11111111 = $11111111 = &286331153 CPU32Bug>DC (4,A0)<CR> 00003004 = $3004 = &12292 CPU32Bug>DC ([4,A0])<CR> 22222222 = $22222222 = &572662306 M68CPU32BUG/D REV 1 3-15...

  • Page 46: Dump S-Records (Du)

    3.9 DUMP S-RECORDS DU [<port><del>]<range><del>[<text><del>][<addr>][<offset>] [;B|W|L] The DU command outputs data from memory in the form of Motorola S-records to a port specified by the user. If <port> is not specified then the S-records are sent to the I/O port (port 0).
  • Page 47 DU command entry. The DU command output is sent to the screen and ProComm copies it into the file TEST.MX. CPU32Bug>DU 4000 4007 ’TEST.MX’ 4000 65000000<ALT-F1><CR> Effective address: 00004000 Effective address: 00004007 S00A0000544553542E4D58E2 S30D650040007001D089A004E7576 S7056500400055 CPU32Bug> M68CPU32BUG/D REV 1 3-17...
  • Page 48 Enter ALT-F1 again to close the log file TEST.MX. The log file contains the extra lines of "Effective address" and "CPU32Bug", but they will not affect subsequent CPU32Bug load (LO) commands, as it keys on the "S" character. The file could be edited to remove the extra lines, if so desired. M68CPU32BUG/D REV 1 3-18...
  • Page 49 D1,D2 00004006 E289 LSR.L #$1,D1 00004008 66FA BNE.B $4004 0000400A E20A LSR.B #$1,D2 0000400C 55C2 SCS.B 0000400E 60FE BRA.B $400E CPU32Bug>RM D0<CR> Initialize D0 and start target program: =00000000 ? 52A9C.<CR> CPU32Bug>GD 4000<CR> Effective address: 00004000 M68CPU32BUG/D REV 1 3-19...
  • Page 50 =00000000 =00000000 =00000000 =00000000 =00005000 =00000000 =00000000 =00000000 =00000000 =00000400 =00000000 =0000FF50 0000400E 60FE BRA.B $400E CPU32Bug> Set PC to start of program and restart target code: CPU32Bug>RM PC<CR> =0000400E ? 4000.<CR> CPU32Bug>GD<CR> Effective address: 00004000 M68CPU32BUG/D REV 1 3-20...

  • Page 51: Go To Next Instruction (Gn)

    Current PC at $6000. Effective address: 00006000 At Breakpoint =00006004 =2700=TR:OFF_S_7 =00000000 =0=F0 =0=F0 =00003830 SSP* =00010000 =00000003 =00000001 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00010000 00006004 61000FFA BSR.W $7000 CPU32Bug> M68CPU32BUG/D REV 1 3-21...
  • Page 52 Current PC at $6000. Effective address: 00006004 At Breakpoint =00006008 =2700=TR:OFF_S_7_..=00000000 =0=F0 =0=F0 =00003830 SSP* =00010000 =00000004 =00000001 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00010000 00006008 2600 MOVE.L D0,D3 CPU32Bug> M68CPU32BUG/D REV 1 3-22...

  • Page 53: Go Execute User Program (Go)

    The following program resides at $4000. CPU32Bug>MD 4000;DI<CR> 00004000 2200 MOVE.L D0,D1 00004002 4282 CLR.L 00004004 D401 ADD.B D1,D2 00004006 E289 LSR.L #$1,D1 00004008 66FA BNE.B $4004 0000400A E20A LSR.B #$1,D2 0000400C 55C2 SCS.B 0000400E 60FE BRA.B $400E CPU32Bug>RM D0<CR> M68CPU32BUG/D REV 1 3-23...
  • Page 54 =0000FC00 SSP* =00010000 =00052A9C =00000000 =000000FF =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00010000 0000400E 60FE BRA.B $400E Remove breakpoints and restart target code. CPU32Bug>NOBR<CR> BREAKPOINTS CPU32Bug>GO 4000<CR> Effective address: 00004000 M68CPU32BUG/D REV 1 3-24...
  • Page 55 Press the ABORT pushbutton on the platform board to exit target code. Exception: ABORT =0000400E =2711=TR:OFF_S_7_X.C =00000000 =5=SD =5=SD =0000FC00 SSP* =00010000 =00052A9C =00000000 =000000FF =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00010000 0000400E 60FE BRA.B $400E M68CPU32BUG/D REV 1 3-25...

  • Page 56: Go To Temporary Breakpoint (Gt)

    $400E CPU32Bug>RM D0<CR> Initialize D0 and set a breakpoint: =00000000 ? 52A9C.<CR> CPU32Bug>BR 400E<CR> BREAKFOINTS 0000400E CPU32Bug> Set PC to beginning of program, set temporary breakpoint, and start target code: CPU32Bug>RM PC<CR> =0000400E ? 4000.<CR> CPU32Bug> M68CPU32BUG/D REV 1 3-26...
  • Page 57 SSP* =00010000 =00052A9C =00000000 =000000FF =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00010000 0000400E 60FE BRA.B $400E Note that a breakpoint from the breakpoint table was encountered before the temproary breakpoint. M68CPU32BUG/D REV 1 3-27...

  • Page 58: Help (H)

    Enable Macro Expansion Listing NOMAL Disable Macro Expansion Listing Memory Display Memory Modify "Alias" for previous command Memory Set Offset Registers Printer Attach NOPA Printer Detach Port Format Register Display RESET Warm/Cold Reset Register Modify Register Set M68CPU32BUG/D REV 1 3-28...
  • Page 59 Go Direct (no breakpoints) Go and Stop after Next Instruction Go to Target Code "Alias" for previous command Go and Insert Temporary Breakpoint Help Facility Load S-Records Macro Define/Display NOMA Macro Delete Macro Edit Enable Macro Expansion Listing M68CPU32BUG/D REV 1 3-29...
  • Page 60 Register Modify Register Set Switch Directory Trace Instruction Trace on Change of Flow Transparent Mode Trace to Temporary Breakpoint Verify S-Records CPU32Bug> To display the command TC, enter: CPU32Bug>HE TC<CR> Trace on Change of Flow CPU32Bug> M68CPU32BUG/D REV 1 3-30...

  • Page 61: Load S-Records From Host (Lo)

    3.15 LOAD S-RECORDS FROM HOST LO [<port><del>][<addr>][;<X/-C/T>][=<text>] Use the LO command to download a Motorola S-records format data file from a host computer to the BCC. The LO command accepts serial data from the host and loads it into on-board memory.
  • Page 62 TRAP #15 disk support. This code is used by the downloaded program to select the appropriate calling convention when executing debugger functions. Since some Motorola debuggers use conventions different from CPU32Bug, they set a different code in D4.
  • Page 63 Since the port number equals the current terminal, two <CR>’s are required to signal CPU32Bug that the download is complete and the terminal emulation program is ready to receive any error messages. Signal download completion. <CR><CR> No error messages. CPU32Bug> M68CPU32BUG/D REV 1 3-33...

  • Page 64: Macro Define/Display/Delete (Mal/Noma)

    Arguments are denoted in macro definitions by embedding a back slash (\) followed by a numerial. As many as ten arguments are permitted. A definition containing a back slash followed by a zero would cause the first argument to that macro to be inserted in place of the "\0" characters. M68CPU32BUG/D REV 1 3-34...
  • Page 65 4280 CLR.L 00004282 1018 MOVE.B (A0)+,D0 00004284 5340 SUBQ.W #$1,D0 00004286 12D8 MOVE.B (A0)+,(A1)+ CPU32Bug> List definitions macro ABC. CPU32Bug>MA ABC<CR> MACRO ABC 010 MD 3000 020 GO \0 CPU32Bug> Delete macro DASM. CPU32Bug>NOMA DASM<CR> CPU32Bug> M68CPU32BUG/D REV 1 3-35...
  • Page 66 CPU32Bug>MA ASM<CR> M=MM \0;DI M=<CR> CPU32Bug> List all macros. CPU32Bug>MA<CR> MACRO ABC 010 MD 3000 020 GO \0 MACRO ASM 010 MD \0;DI CPU32Bug> Delete all macros. CPU32Bug>NOMA<CR> CPU32Bug> List all macros. CPU32Bug>MA<CR> NO MACROS DEFINED CPU32Bug> M68CPU32BUG/D REV 1 3-36...

  • Page 67: Macro Edit (Mae)

    To define new macros, use MA; the MAE command operates only on previously defined macros. Line numbers serve one purpose: specifying the location within a macro definition to perform the editing function. After the editing is complete, the macro definition is displayed with a new set of line numbers. M68CPU32BUG/D REV 1 3-37...
  • Page 68 Replace line 10. CPU32Bug>MAE ABC 10 MD 10+R0<CR> MACRO ABC This line was overwritten. 010 MD 10+R0 020 RD 030 GO \0 CPU32Bug> Delete line 30. CPU32Bug>MAE ABC 30<CR> MACRO ABC 010 MD 10+R0 020 RD CPU32Bug> M68CPU32BUG/D REV 1 3-38...

  • Page 69: Macro Expansion Listing Enable/Disable (Mal/Nomal)

    The NOMAL command is used to suppress the listing of macro lines during execution. The use of MAL and NOMAL is a convenience for the user and in no way interacts with the function of the macros. M68CPU32BUG/D REV 1 3-39...

  • Page 70: Memory Display (Md)

    2800 1842 2900 2846 (..B)..B(..B).(F CPU32Bug><CR> 0000C010 FC20 0050 ED07 9F61 FF00 000A E860 F060 1..Pm..a..h’p’ Assume the following processor state: A2=00003500, D5=00000127. CPU32Bug>md (a2,d5):&19;b<CR> 00003627 4F82 00C5 9B10 337A DF01 6C3D 4B50 0F0F 0..E..3z_.l=KP.. 00003637 31AB 80 CPU32Bug> M68CPU32BUG/D REV 1 3-40...
  • Page 71 0000501E 2C48 MOVE.L A0,A6 00005020 13C7FFFB003A MOVE.B D7,($FFFB003A).L CPU32Bug> NOTE If the address location requested is not displayed, the automatic offset register is non-zero and has been added to the address. See the offset (OF) command. M68CPU32BUG/D REV 1 3-41...

  • Page 72: Memory Modify (Mm)

    NOTE If the address location requested is not displayed, the automatic offset register is non-zero and has been added to the address. See the offset (OF) command. M68CPU32BUG/D REV 1 3-42...
  • Page 73 If an error is found during assembly, the caret symbol (^) appears below the suspect field followed by an error message. The accessed location is redisplayed. Refer to Chapter 4 for additional information about the assembler. M68CPU32BUG/D REV 1 3-43...

  • Page 74: Memory Set (Ms)

    MC68332 TPU registers. For those locations requiring word accessing, use the memory modify (MM) command with the ;W or ;L option. M68CPU32BUG/D REV 1 3-44...

  • Page 75: Offset Registers Display/Modify (Of)

    Step control characters as described in the MM (memory modify) command are supported. Range syntax: [<base address> [<del> <top address>] ] [^|v|=|.] [<base address> [ : <byte count> ] ] [^|v|=|.] M68CPU32BUG/D REV 1 3-45...
  • Page 76 Exit. Notice wrap around to R6. R6 = 00000000 00000000? .<CR> Display location $5000. Shows base and top values for each register. CPU32Bug>M 5000;DI<CR> 00000+R0 41F95445 5354 LEA.L ($54455354).L,A0 .<CR> CPU32Bug>M R0;DI <CR> 00000+R0 41F95445 5354 LEA.L ($54455354).L,A0 .<CR> CPU32Bug> M68CPU32BUG/D REV 1 3-46...
  • Page 77 Display location 0 relative to the default offset register, (R0), i.e. absolute location $5000. CPU32Bug>M 0;DI<CR> 00000+R0 41F95445 5354 LEA.L ($54455354).L,A0 .<CR> CPU32Bug> Display absolute location 0, override the automatic offset. CPU32Bug>M 0+R7;DI <CR> 00000000 FFF8 DC.W $FFF8 .<CR> CPU32Bug> M68CPU32BUG/D REV 1 3-47...

  • Page 78: Printer Attach/Detach (Pa/Nopa)

    CONSOLE DISPLAY: PRINTER OUTPUT: CPU32Bug>PA <CR> (attaching port 1 by default) (printer now attached) CPU32Bug>HE NOPA <CR> CPU32Bug>HE NOPA NOPA Printer detach NOPA Printer detach CPU32Bug>NOPA <CR> CPU32Bug>NOPA (detach all attached printers) (printer now detached) CPU32Bug> M68CPU32BUG/D REV 1 3-48...

  • Page 79: Port Format (Pf)

    Change number of stop bits on port number 0. CPU32Bug>PF 0 <CR> Baud rate [110,300,600,1200,2400,4800,9600,19200] = 9600? < CR> Even, Odd, or No Parity [E,O,N] = N? <CR> Char Width [5,6,7,8] = 8? <CR> New value entered. Stop bits [1,2] = 1? 2<CR> M68CPU32BUG/D REV 1 3-49...

  • Page 80: Port Format Parameters

    8-bit value. ASCII control characters or hexadecimal values are accepted. NOTE Not all combinations of parity type, character width, and stop bits are supported for the BCC "SCI" port, 00. See Appendix C for details. M68CPU32BUG/D REV 1 3-50...

  • Page 81: New Port Assignment

    Name of board? mc68681<CR> Name of port? a<CR> Port base address = $FFFFE000?<CR> Baud rate [110, 300, 600, 1200, 2400, 4800, 9600, 19200] = 9600? .<CR> Note: Aborted, no hardware! OK to proceed (Y/N)? n CPU32Bug> M68CPU32BUG/D REV 1 3-51...

  • Page 82: Register Display (Rd)

    Indicates the first register in a range of registers. <reg2> Indicates the last register in a range of registers. <dname> Indicates a device name. Use <DNAME> to enable or disable all device registers for: Microprocessor Unit M68CPU32BUG/D REV 1 3-52...
  • Page 83 The register mask used by RD is also used by all the exception handler routines, including the trace and breakpoint exception handlers. The MPU registers in ordering sequence are: Number of registers System Registers (PC,SR,USP,SSP,VBR,SFC,DFC) Data Registers (D0-D7) Address Registers (A0-A7) M68CPU32BUG/D REV 1 3-53...
  • Page 84 A number from 0 to 7 indicates the current processor priority level. Condition Codes The bit name (X, N, Z, V, C) appears if the respective bit is set, otherwise a period (.) indicates it is cleared. M68CPU32BUG/D REV 1 3-54...
  • Page 85 SFC =0=F0 =0=F0 =00003830 SSP* =00004000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00004000 00003000 4AFC ILLEGAL CPU32Bug> Note that an equivalent command is ’’RD +PC-A7’’ or ’’RD =PC-A7’’. M68CPU32BUG/D REV 1 3-55...

  • Page 86: Cold/Warm Reset (Reset)

    EXAMPLE CPU32Bug>RESET<CR> Set to warm start. Cold/Warm Start = C (C/W)? W<CR> CPU32Bug> Press the RESET pushbutton. CPU32Bug Debugger/Diagnostics - Version 1.00 (C) Copyright 1991 by Motorola Inc. Warm Start CPU32Bug> M68CPU32BUG/D REV 1 3-56...

  • Page 87: Register Modify (Rm)

    Refer to the MM command. EXAMPLES CPU32Bug>RM D4<CR> Modify register and backup. =12345678? ABCDEF^<CR> Modify register and exit. =00000000? 3000.<CR> CPU32Bug> CPU32Bug>rm sfc<CR> Modify register and re-open. =7=CS ? 1=<CR> Exit =1=UD ? .<CR> CPU32Bug> M68CPU32BUG/D REV 1 3-57...

  • Page 88: Register Set (Rs)

    CPU32Bug>OF R4;A<CR> Set up automatic offset register R4. R4*00000000 00000000? 4000 4FFF<CR> CPU32Bug>RS PC 124<CR> Set PC=$124+R4. =00004124 CPU32Bug>RS A4 32A<CR> Set A4=$32A+R4. =0000432A CPU32Bug>RS A5 400+R7<CR> Set A5 equal to absolute location $400 =00000400 ($400+R7). CPU32Bug> M68CPU32BUG/D REV 1 3-58...

  • Page 89: Switch Directories (Sd)

    EXAMPLES CPU32Bug>SD<CR> The user has changed from the debugger CPU32Diag> directory to the diagnostic directory, as can be seen by the ’’CPU32Diag>’’ prompt CPU32Diag>SD<CR> The user is now back in the debugger CPU32Bug> directory. M68CPU32BUG/D REV 1 3-59...

  • Page 90: Trace (T)

    D1,D2 00007006 E289 LSR.L #$1,D1 00007008 66FA BNE.B $7004 0000700A E20A LSR.B #$1,D2 0000700C 55C2 SCS.B 0000700E 60FE BRA.B $700E CPU32Bug> Initialize PC and D0: CPU32Bug>RM PC<CR> =00008000 ? 7000.<CR> CPU32Bug>RM D0 <CR> =00000000 ? 8F4IC.<CR> M68CPU32BUG/D REV 1 3-60...
  • Page 91 CLR.L CPU32Bug> Trace next instruction: CPU32Bug><CR> =00007004 =2704=TR:OFF_S_7_..Z.. =00000000 SFC =0=F0 =0=F0 =0000382C SSP* =00004000 =0008F41C =0008F41C =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00004000 00007004 D401 ADD.B D1,D2 CPU32Bug> M68CPU32BUG/D REV 1 3-61...
  • Page 92 =00004000 00007006 E289 LSR.L #$1,D1 =00007008 =2700=TR:OFF_S_7_ ..=00000000 SFC =0=F0 =0=F0 =0000382C SSP* =00004000 =0008F41C =00047A0E =0000001C =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00004000 00007008 66FA BNE.B $7004 CPU32Bug> M68CPU32BUG/D REV 1 3-62...

  • Page 93: Trace On Change Of Control Flow

    00007006 E289 LSR.L #$1,D1 00007008 66FA BNE.B $7004 0000700A E20A LSR.B #$1,D2 0000700C 55C2 SCS.B 0000700E 60FE BRA.B $700E CPU32Bug> Initialize PC and D0: CPU32Bug>RM PC <CR> =00008000 ? 7000.<CR> CPU32Bug>RM D0 <CR> =00000000 ? 8F41C.<CR> M68CPU32BUG/D REV 1 3-63...
  • Page 94 =0000382C SSP* =00004000 =0008F41C =00047A0E =0000001C =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00004000 00007004 D401 ADD.B D1,D2 CPU32Bug> Note that the above display also shows the change of flow instruction. M68CPU32BUG/D REV 1 3-64...

  • Page 95: Transparent Mode (Tm)

    Enter TM. CPU32Bug>TM<CR> Escape character: $01=^ A Exit code is always displayed. Exit transparent mode. <^A> Enter TM and set escape character CPU32Bug>TM ^g<CR> to ^ G. Escape character: $07=^ G Exit transparent mode. <^G> CPU32Bug> M68CPU32BUG/D REV 1 3-65...

  • Page 96: Trace To Temporary Breakpoint

    ADD.B D1,D2 00007006 E289 LSR.L #$1,D1 00007008 66FA BNE.B $7004 0000700A E20A LSR.B #$1,D2 0000700C 55C2 SCS.B 0000700E 60FE BRA.B $700E CPU32Bug> Initialize PC and D0: CPU32Bug>RM PC<CR> =00008000 ? 7000.<CR> CPU32Bug>RM D0<CR> =00000000 ? 8F41C.<CR> M68CPU32BUG/D REV 1 3-66...
  • Page 97 00007004 D401 ADD.B D1,D2 At Breakpoint =00007006 =2700=TR:OFF_S_7_..=00000000 SFC =0=F0 =0=F0 =0000382C SSP* =00004000 =0008F41C =0008F41C =0000001C =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00000000 =00004000 00007006 E289 LSR.L #$1,D1 CPU32Bug> M68CPU32BUG/D REV 1 3-67...

  • Page 98: Verify S-Records Against Memory (Ve)

    The VE command accepts serial data from a host system in the form of a Motorola S-records file and compares it to data already in memory. If the data does not compare, then the user is alerted via information sent to the terminal screen.
  • Page 99 EXAMPLES This short program was developed on a host system. * Test Program 65004000 $65004000 65004000 7001 MOVEQ.L #1,D0 65004002 D088 ADD.L A0,D0 65004004 4A00 TST.B 65004006 4E75 ****** TOTAL ERRORS ****** TOTAL WARNINGS M68CPU32BUG/D REV 1 3-69...
  • Page 100 Signal verfication complete. <CR><CR> Verify passes. CPU32Bug> The verification passes. The program stored in memory was the same as that in the downloaded S-record file. M68CPU32BUG/D REV 1 3-70...
  • Page 101 Signal verification completion. <CR><CR> Record did not verify. S30D65004000------88--------77 CPU32Bug> The byte which was changed in memory does not compare with the corresponding byte in the S- record. M68CPU32BUG/D REV 1 3-71...
  • Page 102 DEBUG MONITOR COMMANDS M68CPU32BUG/D REV 1 3-72...

  • Page 103: Chapter 4 Assembler/Disassembler

    Normally, assembly language can contain mnemonic directives which specify assembler auxiliary action. The CPU32Bug assembler recognizes only two directives: DC.W (define constant) and SYSCALL. These two directives define data within the program and make CPU32Bug utility calls (refer to paragraphs 4.2.3 and 4.2.4, respectively). M68CPU32BUG/D...

  • Page 104: M68300 Family Resident Structured Assembler Comparison

    A source program is a sequence of source statements arranged in a logical manner to perform predetermined tasks. Each source statement occupies a line and must be either an executable instruction, a DC.W directive, or a SYSCALL assembler directive. Each source statement follows a consistent source line format. M68CPU32BUG/D...

  • Page 105: Source Line Format

    Add the entire 32-bit (longword) contents of A3 to D3. ADD.L A3,D3 EXAMPLE Illegal Illegal size specification (.B not allowed in instruction SUBA). This SUBA.B #5,A1 instruction would have subtracted the value 5 from the low order byte of A1; byte operations on address registers are not allowed. M68CPU32BUG/D...

  • Page 106: Operand Field

    The BT form (branch conditionally true) has the same opcode as the BRA instruction. Also, DBRA (decrement and branch always) and DBF (never true, decrement, and branch) mnemonics are different forms for the same instruction. In each case, the assembler accepts both forms. M68CPU32BUG/D...

  • Page 107: Mnemonics And Delimiters

    Source Function Code Register Destination Function Code Register D0-D7 Data Registers A0-A7 Address Registers - Address register A7 represents the active system stack pointer, that is, either USP or SSP, as specified by the S bit of the status register M68CPU32BUG/D...

  • Page 108: Character Set

    The asterisk (*) character indicates current location. 4.2.2 Addressing Modes Effective address modes, combined with operation codes, define the particular function performed by a given instruction. Effective addressing and data organization are described in detail in the CPU32 Reference Manual. M68CPU32BUG/D...

  • Page 109: Cpu32Bug Assembler Addressing Modes

    The user may use an expression in any numeric field of these addressing modes. The assembler has a built in expression evaluator that supports the following operand types and operators: Binary numbers (%10 ) Octal numbers (@76543210) Decimal numbers (&9876543210) Hexadecimal numbers ($FEDCBA9876543210) String literals (’CHAR’ ) Offset registers (R0-R7) Program counter M68CPU32BUG/D...
  • Page 110 For parsing algebraic expressions, the order of parsing is <OPERAND> <OPERATOR> <OPERAND> <OPERATOR> with a possible left or right parenthesis. Given the above order, the assembler can distinguish by placement which definition to use. For example: Means Means Means *&&16 Means &16 M68CPU32BUG/D...

  • Page 111: Define Constant Directive (Dc.w)

    (’ . . . ’). Each character (7 bits) is assigned to a byte of memory with the eighth bit (MSB) always equal to zero. If only one byte is entered, the byte is right justified. A maximum of two ASCII characters may be entered for each DC.W directive. M68CPU32BUG/D...

  • Page 112: System Call Directive (Syscall)

    Also, editing is accomplished by retyping an entirely new source line. Add or delete lines by moving a block of memory data to free up or delete the appropriate number of locations (refer to the BM command). M68CPU32BUG/D 4-10...

  • Page 113: Executing The Assembler/Disassembler

    A period (.) is used to exit the MM command. If an error occurs during line assembly, the assembler displays the line unassembled with an error message. The location being accessed is redisplayed: CPU32Bug>MM 6000;di <CR> 00006000 528B ADDQ.L #$1,A3? LEA.L 5(A0,D8),A4<CR> LEA.L 5(A0,D8),A4 BAD COMBINATION OF COMMAND, OPERANDS 00006000 528B ADDQ.L #$1,A3? M68CPU32BUG/D 4-11...

  • Page 114: Entering Branch And Jump Addresses

    Note again, that the listing may not correspond exactly to the program as entered. As discussed in paragraph 4.2.1.3, the disassembler displays in signed hexadecimal any number it interprets as an offset of an address register; all other numbers are displayed in unsigned hexadecimal. M68CPU32BUG/D 4-12...

  • Page 115: Chapter 5 System Calls

    In some of the examples shown in the following descriptions, a SYSCALL macro is used with the Motorola Macro Assembler (M68MASM) for MS-DOS/PC-DOS machines. This macro automatically assembles the TRAP #15 call followed by the define constant for the function code.

  • Page 116: Input/Output String Formats

    It is necessary to create an equate file with the routine names equated to their respective codes, or download the archive file C32SCALL.ARC from the Motorola FREEWARE Bulletin Board (BBS). For more information on the FREEWARE BBS, reference customer letter M68xxxEVx/L2.

  • Page 117: Cpu32Bug System Call Routines

    $0042 Read timer .TM_STR0 $0041 Start timer at T=0 .WRITD $0028 Output string with data (pointer/count format) .WRITDLN $0025 Output line with data (pointer/count format) .WRITE $0023 Output string (pointer/count format) .WRITELN $0024 Output line (pointer/count format) M68CPU32BUG/D REV 1...
  • Page 118 Exit Conditions: SP ==> Decimal number (2 Most Significant Digits) <long> (8 Most Significant Digits) <long> EXAMPLE Allocate space for result SUBQ.L #8,A7 Load hex number MOVE.L D0,-(A7) SYSCALL .BINDEC Call .BINDEC Load result into D1/D2 MOVEM.L (A7)+,D1/D2 M68CPU32BUG/D REV 1...

  • Page 119: Parse Value, Assign To Variable (.Changev)

    EXAMPLE PROMPT DC.B $14,’COUNT = |10,8|’ Point to prompt string GETCOUNT PROMPT(PC) Point to variable to change COUNT Point to buffer BUFFER Point to offset into buffer POINT Make the system call SYSCALL .CHANGEV COUNT changed, return M68CPU32BUG/D REV 1...
  • Page 120 For example, if the string 5 is entered in response to the prompt. COUNT = 3? 5<CR> COUNT = 5 If in the previous example nothing had been entered at the prompt, COUNT would retain its prior value. COUNT = 3? <CR> COUNT = 3 M68CPU32BUG/D REV 1...

  • Page 121: Check For Break (.Chkbrk)

    Returns zero (0) status in condition code register if break status is detected at the default input port. Entry Conditions: No arguments or stack allocation required Exit Conditions: Z flag set in CCR if break detected EXAMPLE SYSCALL .CHKBRK BREAK M68CPU32BUG/D REV 1...

  • Page 122: Timer Delay Function (.Delay)

    The timer keeps running after the delay and parameters are removed from the stack. EXAMPLE Initialize timer SYSCALL .TM INI Start timer SYSCALL .TM_STR0 Load a 1500 interrupt pulse delay PEA.L &1500 SYSCALL .DELAY Load a 50000 interrupt pulse delay PEA.L &50000 SYSCALL .DELAY M68CPU32BUG/D REV 1...

  • Page 123: Unsigned 32 X 32 Bit Divide (.Divu32)

    32-bit quotient (result from division) EXAMPLE Divide D0 by D1, load result into D2. Allocate space for result SUBQ.L #4,A7 MOVE.L D0,-(A7) Push dividend Push divisor MOVE.L D1,-(A7) Divide D0 by D1 SYSCALL .DIVU32 Get quotient MOVE.L (A7)+,D2 M68CPU32BUG/D REV 1...

  • Page 124: Erase Line (.Erasln)

    .ERASLN TRAP CODE: $0027 Use .ERASLN to erase the line at the present cursor position. Entry Conditions: No arguments required. Exit Conditions: The cursor is positioned at the beginning of a blank line. EXAMPLE SYSCALL .ERASLN M68CPU32BUG/D REV 1 5-10...

  • Page 125: Input Character Routine (.Inchr)

    Entry Conditions: SP ==> Space for character <byte> Word fill <byte> Exit Conditions: SP ==> Character <byte> Word fill <byte> EXAMPLE Allocate space for result SUBQ.L #2,A7 Call .INCHR SYSCALL .INCHR Load character in D0 MOVE.B (A7)+,D0 M68CPU32BUG/D REV 1 5-11...

  • Page 126: Input Line Routine (.Inln)

    A line is a string of characters terminated by a carriage return (<CR>). The maximum allowed size is 254 characters. The terminating <CR> is not included in the string. See Terminal Input/Output Control character processing as described in Chapter M68CPU32BUG/D REV 1 5-12...

  • Page 127: Input Serial Port Status (.Instat)

    Z (zero) = 1 if the receiver buffer is empty EXAMPLE Any characters? LOOP SYSCALL .INSTAT If no, branch BEQ.S EMPTY If yes, then read them in buffer SUBQ.L #2,A7 SYSCALL .INCHR MOVE.B (A7)+,(A0)+ BRA.S LOOP Check for more EMPTY M68CPU32BUG/D REV 1 5-13...

  • Page 128: Unsigned 32 X 32 Bit Multiply (.Mulu32)

    32-bit product (result from multiplication) EXAMPLE Multiply D0 by D1, load result into D2. Allocate space for result SUBQ.L #4,A7 Push multiplicand MOVE.L D0,-(A7) Push multiplier MOVE.L D1,-(A7) Multiply D0 by D1 SYSCALL .MULU32 Get product MOVE.L (A7)+,D2 M68CPU32BUG/D REV 1 5-14...

  • Page 129: Output Character Routine (.Outchr)

    Word fill <byte> (Placed automatically by the MCU) Exit Conditions: SP ==> Top of stack Character is sent to the default I/O port. EXAMPLE Send character in D0 MOVE.B D0,-(A7) To default output port SYSCALL .OUTCHR M68CPU32BUG/D REV 1 5-15...

  • Page 130: Output String Using Pointers (.Outln/Outstr)

    +4 Address of last character + 1 <long> Exit Conditions: SP ==> Top of stack EXAMPLE If A0 = start of string and A1 = end of string+1 Load pointers to string and print it MOVEM.L A0/A1,-(A7) SYSCALL .OUTSTR M68CPU32BUG/D REV 1 5-16...
  • Page 131 TRAP CODE: $0026 .PCRLF sends a carriage return and a line feed to the default output port. Entry Conditions: No arguments or stack allocation required. Exit Conditions: None EXAMPLE SYSCALL .PCRLF Output a carriage return and line feed M68CPU32BUG/D REV 1 5-17...

  • Page 132: Read Line To Fixed-Length Buffer (.Readln)

    The caller must allocate 256 bytes for a buffer. Input are limited to 254 characters. <CR> and <LF> are sent to default output following echo of the input. See Terminal Input/Output Control character processing as described in Chapter 1. M68CPU32BUG/D REV 1 5-18...

  • Page 133: Read String Into Variable-Length Buffer (.Readstr)

    This routine allows the caller to define the maximum character input length (254 characters). If more than 254 characters are entered, then the buffer input is truncated. See Terminal Input/Output Control character processing as described in Chapter M68CPU32BUG/D REV 1 5-19...

  • Page 134: Return To Cpu32Bug (.Return)

    Then the target state is saved in the register image area. Finally, the routine returns to CPU32Bug. Entry Conditions: No arguments required. Exit Conditions: Control is returned to CPU32Bug. EXAMPLE Return to CPU32Bug SYSCALL .RETURN M68CPU32BUG/D REV 1 5-20...

  • Page 135: Send Break (.Sndbrk)

    5.2.17 Send Break SYSCALL .SNDBRK TRAP CODE: $0029 Use .SNDBRK to send a break to the default output port. Entry Conditions: No arguments or stack allocation required Exit Conditions: The default port is sent ’’break’’. EXAMPLE SYSCALL .SNDBRK M68CPU32BUG/D REV 1 5-21...

  • Page 136: Compare Two Strings (.Strcmp)

    Push address of one string (A1) Push address of the other string (A2) Compare the strings SYSCALL .STRCMP Pop boolean flag into data register MOVE.L (A7)+,D0 TST.B Check boolean flag Branch if strings are identical ARE SAME M68CPU32BUG/D REV 1 5-22...

  • Page 137: Timer Initialization (.Tm_Ini)

    125 milliseconds. Use this routine the first time the timer functions are used. Entry Conditions: No arguments required. Exit Conditions Different From Entry: Periodic interrupt timer is stopped (no interrupts) and initialized for future operation. EXAMPLE Initialize timer SYSCALL .TM_INI M68CPU32BUG/D REV 1 5-23...

  • Page 138: Read Timer (.Tm_Rd)

    Exit Conditions Different From Entry:. SP ==> Time (number of interrupt pulses) <long>. The timer keeps running after the read. EXAMPLE Allocate space for result SUBQ.L #4,A7 Read timer SYSCALL .TM_RD Load interrupt pulse count MOVE.L (A7)+,D0 M68CPU32BUG/D REV 1 5-24...

  • Page 139: Start Timer At T=0 (.Tm_Str0)

    If the value of PICR is not equal to the power-up default value, $000F, the old vector number is restored to the default CPU32Bug value. EXAMPLES SYSCALL .TM_STR0 Reset the timer to zero and start it with the default values. MOVE.L #0,-(A7) SYSCALL .TM_STR0 M68CPU32BUG/D REV 1 5-25...
  • Page 140 .TM_STR0 usec/interrupt). Reset the timer to zero and start it with the control value MOVE.L #$054400A0,-(A7) (PICR) of $0544 (level 5, vector 68 = $44) and a period SYSCALL .TM_STR0 value (PITR) of $00A0 (=19.5 msec/interrupt). M68CPU32BUG/D REV 1 5-26...

  • Page 141: Output String With Data (.Writd/Writln)

    A separate data stack or data list arranged as follows: Data list pointer => Data for 1st variable in string <long> Data for next variable <long> Data for next variable <long> Exit Conditions: SP ==> Top of stack (parameter bytes removed) M68CPU32BUG/D REV 1 5-27...
  • Page 142 (see example above) to de-allocate space in the data stack. If it is necessary for the space in the data stack to be de-allocated, it must be done using the call routine, as shown in the above example. M68CPU32BUG/D REV 1 5-28...

  • Page 143: Output String Using Character Count (.Write/Writeln)

    Top of stack (parameter bytes removed) EXAMPLE "MOTOROLA " MESSAGE1 DC.B "QUALITY!" MESSAGE2 DC.B Push address of string MESSAGE1(PC) Use TRAP #15 macro SYSCALL .WRITE MESSAGE2(PC) Push address of other string Invoke function again SYSCALL .WRITE M68CPU32BUG/D REV 1 5-29...
  • Page 144 Using .WRITELN instead of .WRITE outputs this message: MOTOROLA QUALITY! NOTE The string must be formatted such that the first byte (the byte pointed to by the passed address) contains the byte count of the string (pointer/count format – see 5.1.2). M68CPU32BUG/D REV 1 5-30...

  • Page 145: Chapter 6 Diagnostic Firmware Guide

    MT A ! MT B. Spaces are not required but are shown here for legibility. Several commands may be combined on one line. Commands are listed in the diagnostic directory. Some commands have sub-commands which are listed in the directory for that particular command (see example below). CPU A SUB-COMMAND COMMAND M68CPU32BUG/D REV 1...

  • Page 146: Help (He)

    Use the Loop-on-error mode (LE) to endlessly repeat a test at the point where an error is detected. This is useful when using a logic analyzer to trouble-shoot test failures. Enter LE and the test name to loop on errors encountered during the test. M68CPU32BUG/D REV 1...

  • Page 147: Stop-On-Error Mode (Se)

    A count of the number of passes in loop-continue mode is kept by the monitor. This count is displayed with other information at the conclusion of each pass. To display this information without using LC, enter DP. M68CPU32BUG/D REV 1...

  • Page 148: Zero Pass Count (Zp)

    Switch to diagnostic directory CPU32Bug>SD<CR> Prompts for address and data to which to CPU32Diag>WR.W<CR> write word value. Writes $E6 to $40FC CPU32Diag>WR.B 40FC E6<CR> Writes $43F6 to $800C CPU32Diag>WR.W 800C 43F6<CR> Writes $F8432191 to $54F0 CPU32Diag>WR.L 54F0 F8432191<CR> M68CPU32BUG/D REV 1...

  • Page 149: Read Loop

    $. To write $00 out to address $10000 and read back, enter WR.B 10000 00. The system prompts the user if either or both parameters are omitted. EXAMPLE Writes longword $FFFFFFFF to location $8000 and CPU32Diag>WR.W 8000 FFFFFFFF<CR> reads it back M68CPU32BUG/D REV 1...

  • Page 150: Cpu Tests For The Mcu (Cpu)

    Table 6-1. MCU CPU Diagnostic Tests Monitor Command Title CPU A Register Test CPU B Instruction Test CPU C Address Mode Test CPU D Exception Processing Test The normal procedure for correcting a CPU error is to replace the MCU micro-controller unit. M68CPU32BUG/D REV 1...

  • Page 151: Register Test (Cpu A)

    Failed SR register check Failed USP/VBR/CAAR register check Failed CACR register check Failed AO-A4 register check Failed A5-A7 register check If all parts of the test are completed correctly, then the test passes. CPU Register test....Running ----------> PASSED M68CPU32BUG/D REV 1...

  • Page 152: Instruction Test (Cpu B)

    Failed MULU or DIVU instruction check Failed BSET or BCLR instruction check Failed LSR instruction check Failed LSL instruction check If all parts of the test are completed correctly, then the test passes. CPU Instruction Test....Running ----------> PASSED M68CPU32BUG/D REV 1...

  • Page 153: Address Mode Test (Cpu C)

    Failed Post increment check Failed Pre decrement check Failed Indirect Addressing with Index check Unexpected Bus Error at $XXXXXXXX If all parts of the test are completed correctly, then the test passes. CPU Address Mode test....Running ----------> PASSED M68CPU32BUG/D REV 1...

  • Page 154: Exception Processing Test (Cpu D)

    However, if the failure involves taking an exception different from that being tested, the display is: CPU Exception Processing Test..Running ---------->..FAILED Unexpected exception taken to Vector # XXX If all parts of the test are completed correctly, then the test passes. CPU Exception Processing Test..Running ----------> PASSED M68CPU32BUG/D REV 1 6-10...

  • Page 155: Memory Tests (Mt)

    MT G Refresh Test MT H Random Byte Test MT I Program Test MT J TAS Test The following hardware is required to perform these tests. M68300EVK - Module being tested Video display terminal or host computer M68CPU32BUG/D REV 1 6-11...
  • Page 156 Each numeral in the heading is the one’s digit of the bit position. For example, the leftmost bad bit at test address $10004 has the numeral 2 over it. Because this is the second 2 from the right, the bit position is read 12 in decimal (base 10). M68CPU32BUG/D REV 1 6-12...

  • Page 157: Set Function Code (Mt A)

    Function Code=<new value> CPU32Diag> This command may be used to display the current value without changing it by pressing a carriage return <CR> without entering the new value. CPU32Diag>MT A<CR> Function Code=<current value> ?<CR> Function Code=<current value> CPU32Diag> M68CPU32BUG/D REV 1 6-13...

  • Page 158: Set Start Address (Mt B)

    The start address is never allowed higher in memory than the stop address. These changes occur before another command is processed by the monitor. M68CPU32BUG/D REV 1 6-14...

  • Page 159: Set Stop Address (Mt C)

    The stop address is never allowed to be lower in memory than the start address. These changes occur before another command is processed by the monitor. M68CPU32BUG/D REV 1 6-15...

  • Page 160: Set Bus Data Width (Mt D)

    CPU32Diag>MT D [new value: 0 for 16, 1 for 32] MT D selects either 16-bit or 32-bit bus data accesses during the M68CPU32Bug MT memory tests. The width is selected by entering zero for 16 bits or one for 32 bits.

  • Page 161: March Address Test (Mt E)

    If an error is encountered, then the memory location and other related information are displayed. MT March Addr. Test....Running ---------->..FAILED (error-related information) If no errors are encountered, then the display appears as follows: MT March Addr. Test....Running ----------> PASSED M68CPU32BUG/D REV 1 6-17...

  • Page 162: Walk A Bit Test (Mt F)

    If an error is encountered, then the memory location and other related information are displayed. MT Walk a bit Test ....Running ---------->..FAILED (error-related information) If no errors are encountered, then the display appears as follows: MT Walk a bit Test ....Running ----------> PASSED M68CPU32BUG/D REV 1 6-18...

  • Page 163: Refresh Test (Mt G)

    If an error is encountered, then the memory location and other related information are displayed. MT Refresh Test....Running ---------->..FAILED (error-related information) If no errors are encountered, then the display appears as follows: MT Refresh Test....Running ----------> PASSED M68CPU32BUG/D REV 1 6-19...

  • Page 164: Random Byte Test (Mt H)

    If an error occurs, then the memory location and other related information are displayed. MT Random Byte Test....Running ---------->..FAILED (error-related information) If no errors occur, then the display appears as follows: MT Random Byte Test....Running ----------> PASSED M68CPU32BUG/D REV 1 6-20...

  • Page 165: Program Test (Mt I)

    If the program (in RAM) detects any errors, then the location of the error and other information is displayed. MT Program Test....Running ---------->..FAILED (error-related information) If no errors occur, then the display appears as follows: MT Program Test....Running ----------> PASSED M68CPU32BUG/D REV 1 6-21...

  • Page 166: Test And Set Test (Mt J)

    If an error occurs, then the memory location and other related information are displayed. MT TAS Test......Running ---------->..FAILED (error-related information) If no errors occur, then the display appears as follows: MT TAS Test......Running ----------> PASSED M68CPU32BUG/D REV 1 6-22...

  • Page 167: Bus Error Test (Berr)

    No Bus Error when reading from BAD address space No Bus Error when writing to BAD address space If all three parts of the test are completed correctly, then the test passes. BERR Bus Error Test.....Running ----------> PASSED M68CPU32BUG/D REV 1 6-23...
  • Page 168 DIAGNOSTIC FIRMWARE GUIDE M68CPU32BUG/D REV 1 6-24...

  • Page 169: Appendix A S-Record Information

    28 (56 printable characters in the S-record). checksum The least significant byte of the one’s complement of the sum of the values represented by the pairs of characters making up the records length, address, and the code/data fields. M68CPU32BUG REV 1...

  • Page 170: S-Record Types

    Eight types of S-records have been defined to accommodate the several needs of the encoding, transportation and decoding functions. The various Motorola upload, download and other records transportation control programs, as well as cross assemblers, linkers and other file-creating or debugging programs, utilize only those S-records which serve the purpose of the program.

  • Page 171: S-Records Creation

    S-record type S1, indicating that it is a code/data record to be loaded/verified at a 2-byte address. Hexadecimal 13 (decimal 19), indicating that 19 character pairs, representing 19 bytes of binary data, follow. Four-character, 2-byte, address field; hexadecimal address 0000, where the data which follows is to be loaded. M68CPU32BUG REV 1...
  • Page 172 TYPE LENGTH ADDRESS CODE/DATA CHECKSUM ••• ••• 0101 0011 0011 0001 0011 0001 0011 0011 0011 0000 0011 0000 0011 0000 0011 0000 0011 0010 0011 1000 0011 0101 0100 0110 ••• 0011 0010 0100 0001 M68CPU32BUG REV 1...

  • Page 173: Appendix B Self-Test Error Messages

    ERROR $12 @ $000EXXXX, CONFIDENCE TEST FAILED MUL, DIV ERROR $13 @ $000EXXXX, CONFIDENCE TEST FAILED BSET, BCLR ERROR $14 @ $000EXXXX, CONFIDENCE TEST FAILED ERROR $15 @ $000EXXXX, CONFIDENCE TEST FAILED ERROR $16 @ $000EXXXX, CONFIDENCE TEST FAILED M68CPU32BUG REV 1...
  • Page 174 ERROR $40 @ $000EXXXX, CONFIDENCE TEST FAILED Absolute, immediate ERROR $41 @ $000EXXXX, CONFIDENCE TEST FAILED Address indirect ERROR $42 @ $000EXXXX, CONFIDENCE TEST FAILED Postincrement, pre- decrement ERROR $43 @ $000EXXXX, CONFIDENCE TEST FAILED Address indirect with index M68CPU32BUG REV 1...

  • Page 175: Appendix C User Customization

    This appendix details the customization features of CPU32Bug. An IBM-PC or compatible host computer with the Motorola program BCC EPROM utility (PROGBCC) is required to reprogram the EPROM on the BCC. This appendix assumes the user is using the ProComm terminal emulation program on the host computer to communicate with CPU32Bug and is familiar with the following;...

  • Page 176: Cpu32Bug Customization

    "Effective address" lines at the beginning of the file and the CPU32Bug> prompt at the end, but it is not required. If the two S-record files are concatenated into one file, edit the first file to remove the S8 termination record at the end of the file. M68CPU32BUG REV 1...
  • Page 177 <CR><CR> Verify passes. CPU32Bug> Follow the PROGBCC utility (available on FREEWARE) directions for reprogramming the BCC EPROM using the two S-record files, C32B1.MX and C32B23.MX. M68CPU32BUG REV 1...
  • Page 178 11. On the host computer, enter the following commands to update the two CPU32Bug S- record files so they may be properly archived to a floppy disk for safe keeping: C>DEL TMP.MX<CR> C>DEL C32B1.MX<CR> C>RENAME C32B1C.MX C32B1.MX<CR> C>COPY C32B*.MX A:<CR> 12. The customization procedure is now complete. M68CPU32BUG REV 1...

  • Page 179: Customization Table

    $32-33 $680F .CSOR8 option register value $34-35 $0000 .CSBAR9 base address register value and $36-37 $0000 .CSOR9 option register value $38-39 $0103 .CSBAR10 CS10 base address register value and $3A-3B $5030 .CSOR10 option register value M68CPU32BUG REV 1...
  • Page 180 $DFFF MCR_AND Value ANDed with result value after MCR_OR and stored back into MCR. If bit 6 (MM bit)of MCR_AND = 0, then module register block is placed at $7FF000. Otherwise it is placed at $FFF000 (default). M68CPU32BUG REV 1...
  • Page 181 Crystal frequency in Hz (8000 = 32,768). SCI baud rates are calculated using this value. $74-77 $FFFFFFFF FEXTAL External clock frequency (in hertz). Only used when MODCK is held low during RESET to enable the EXTAL pin. SCI baud rates are calculated using this value. M68CPU32BUG REV 1...
  • Page 182 1200 = $04B0 = $0258 = $012C .PARITY Parity selection (see Table C-2): None = $00 Even = $45 = ’E’ = $4F = ’O’ .DATA Data bits (see Table C-2): 8-bits = $08 7-bits = $07 M68CPU32BUG REV 1...
  • Page 183 Periodic interrupt control register value: Default value is set for level 6, vect. 66. $8E-8F $0102 .PITR Periodic interrupt timing register value: Controls the "tick" time for the SYSCALL timing functions ($4X). Default value is set for 125 milliseconds. M68CPU32BUG REV 1...
  • Page 184 Entry: D7.B = 0 for no self-test errors, else it equals the error code number (see Appendix B). D7:31-8 = power up status flags Never returns. $B4-B9 all $FF’s BRA.L <reserved> $BA-BF all $FF’s BRA.L <reserved> $C0-CF all $FF’s <reserved> M68CPU32BUG REV 1 C-10...
  • Page 185 If the data size is BYTE (s=1) and there are an even number of <DATA> elements (n+1 is odd), then one filler byte is added so the next Table entry will start on an even address (word) boundary. M68CPU32BUG REV 1 C-11...
  • Page 186 The routine will also terminate before any attempt is made to read table information past the end of the table. Thus the user can completely fill the table without having to have a termination entry whose <ADDR> equals FILL_L. M68CPU32BUG REV 1 C-12...
  • Page 187 $170- SIGNON Text string in SYSCALL .WRITE format. Default values shown in MASM assembly language format below except "^" has been substituted for each space character (" ") to show exact spacing. The Motorola copyright must be preserved. SIGNON DC.B SIGN$2-SIGN$1 Char.

  • Page 188: Communication Formats

    CPU32Bug. Table C-2. MCU SCI Communication Formats Character Width Parity Stop bit Description None Invalid port setting None Even Even None None Even Even Invalid port setting Invalid port setting M68CPU32BUG REV 1 C-14...

  • Page 189: Bcc Rev. A Chip Selection Summary

    PFB U3 write enable for MSB=UPPER=EVEN RAM. cut/jump U3-27 from CS4 to CS10 required. NOTE U1/U3 = 120 nsec RAM with fast termination. U2/U4 = ROM laid-out wrong, can only be configured as 120 nsec RAM. M68CPU32BUG REV 1 C-15...

  • Page 190: Bcc Rev. B Chip Selection Summary

    MSB/LSB=BOTH RAMS PFB U1 write enable for LSB=LOWER=ODD CS10 PFB U3 write enable for MSB=UPPER=EVEN NOTE U1/U3 = 120 nsec RAM with fast termination. U2/U4 = 250 nsec EPROM (or jumper selectable as RAM). M68CPU32BUG REV 1 C-16...

  • Page 191: Bcc Rev. C Chip Selection Summary

    CS2 to CS5 required. PFB U2 read enable for LSB=LOWER=ODD RAM/EPROM PFB U4 read enable for MSB=UPPER=EVEN RAM/EPROM PFB U1/U3 read enable for MSB/LSB=BOTH PFB U1 write enable for LSB=LOWER=ODD CS10 PFB U3 write enable for MSB=UPPER=EVEN M68CPU32BUG REV 1 C-17...

  • Page 192: Platform Board (Pfb) Rev. C Compatibility

    BOARD REVISION Rev. A Rev. B Rev. A Rev. B BCC Rev. A BCC Rev. B BCC Rev. C (1) The default when no jumper block is installed is Rev. B. M68CPU32BUG REV 1 C-18...

  • Page 193: Cpu32Bug Questions And Answers

    A: Change the CODESIZE parameter to $10000 so only the first half of the BCC EPROM is used in calculating the checksum. Or, disable the checksum by setting it to the unprogrammed state of all $FF’s, i.e., set the CHECKSUM parameter to $FFFF. M68CPU32BUG REV 1 C-19...
  • Page 194 VLSI UART device, such as found in the IBM-PC, might tollerate baud rate error differences up to 5%. In summary, all baud rates may not be available depending upon the system clock rate used. M68CPU32BUG REV 1 C-20...
  • Page 195 CPU32Bug commands may fail to complete their tasks before the watchdog can be serviced, which causes a system reset. If the value is too small, the CPU32Bug signon message will never appear, as the MCU will be in a state of chronic reset. M68CPU32BUG REV 1 C-21...
  • Page 196 A: Use the ROM Auto Boot Vectors (RB_SP and RB_PC) to implement a turn-key system whereby CPU32Bug initializes itself and then loads the stack pointer (SSP) and program counter (PC), thus starting execution of the user’s program. M68CPU32BUG REV 1 C-22...

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