Ultra Dma Data Transfer Timing - Hitachi DK23DA-30F - 30 GB Hard Drive Specifications

6.4.2 Ultra DMA Data Transfer Timing

Figures 6-8 through 6-12 and 6-13 through 17 define the timings associated with all phases of Ultra DMA data
transfer.
DM AR Q
(device)
DM AC K-
(host)
ST O P
(host)
HD M ARDY-
(host)
DSTR O BE
(device)
DD (15:0)
DA0, DA1, DA2,
CS0-, CS1-
Note: The definitions for the STOP, HDMARDY and DSTROBE signal lines are not in effect until DMARQ
and DMACK are asserted.
Mode 0(ns) Mode 1(ns) Mode 2(ns) Mode3(ns) Mode4(ns) Mode5(ns)
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
t 70
DVS
t 6.2
DVH
t 230
FS
t 0
UI
t 10
AZ
t 0
ZAD
t 20 70
ENV
t 0
ZIORDY
t 0
ZFS
t 70
DZFS
t 20
ACK
K6602705
Rev.3
08.20.01
Figure 6-8 Initiating an Ultra DMA Read
t
U I
t t
ACK
t
t
ACK
ENV
t
ZIOR DY
t
AZ
t
ACK
48 31
6.2 6.2
200 170
0 0
10 10
0 0
20 70 20 70
0 0
0 0
48 31
20 20
t
FS
ENV
t
ZAD
t
FS
t
ZAD
t
ZFS
t
D ZFS
t
D VS
20 6.7
6.2 6.2
130 120
0 0
10 10
0 0
20 55 20 55
0 0
0 0
20 6.7
20 20
- 99 -
t
D VH
Description
4.8 Data valid setup time at sender
4.8 Data valid hold time at sender
90 First strobe
0 Unlimited interlock
Maximum time allowed for
10
output drivers to release
0 Maximum delay time for output
drivers turning on
Envelope time
20 50
Minimum time waiting before
0
driving IORDY
Time from STROBE output
35
released-to-driving until the first
transition of critical timing
Time from data output released-
25
to-driving until the first transition
of critical timing
Setup and hold times before
20
assertion and negation of
DMACK_