Interface Signal Timing; Data Transfer Timing - Hitachi DK23DA-30F - 30 GB Hard Drive Specifications

6.4 Interface Signal Timing

6.4.1 Data Transfer Timing

Figures 6-4, 6-5, and 6-7 show the timing for asserting interface signals for transferring 16-bit and
8-bit data.
Addr Valid *1
DIOR-/DIOW-
Write Data Valid *2
Read Data Valid *2
IOCS16-
*1 Device Address consists of signals CS0-, CS1-, and DA2-0
*2 Data consists of DD0-15(16 bit) or DD0-7(8 bit)
SYMBOL
t
0
t
1
t
2
t
i
2
t
3
t
4
t
5
t
6
t
6Z
t
7
t
8
t
9
K6602705
Rev.3
08.20.01
Figure 6-4 PIO Data Transfer Timing(Mode 4)
t
1
t
7
Description
Cycle Time
Address Valid to DIOR-/DIOW- Setup
DIOR-/DIOW- Pulse Width
DIOR-/DIOW- Recovery
DIOW- Data Setup
DIOW- Data Hold
DIOR- Data Setup
DIOR- Data Hold
DIOR- Data tristate
Addr Valid To IOCS16- Assertion(MAX)
Addr Valid To IOCS16- Negation (MAX)
DIOR-/DIOW- to Address Valid Hold
t
0
t
t
9
2
t
2i
t
t 4
3
t
6
t
5
t
6Z
MIN(ns)
120
25
70
25
20
10
20
5
10
- 96 -
t
8
MAX(ns)
30
40
30