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ELECTRICAL DATA
V
DD
nRESET
Figure 17-2. Stop Mode Release Timing When Initiated by a RESET
°
= −25
(T
C ~ + 85
A
Parameter
Input
capacitance
Output
capacitance
I/O capacitance
17-6
Execution of
STOP Instrction
NOTE:
t
WAIT
Table 17-4. Input/Output Capacitance
°
C, V
= 0 V)
DD
Symbol
Conditions
C
f = 1 MHz; unmeasured pins
IN
are connected to V
C
OUT
C
IO
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
Stop Mode
Data Retention Mode
V
DDDR
0.2 V
is the same as 16 × 1/BT clock.
SS
Oscillation
RESET
Stabilization
Occurs
TIme
0.8 V
DD
t
DD
WAIT
Min
Typ
−
−
Normal
Operating Mode
Max
Unit
10
pF
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