Sharp DV-SL700W Service Manual page 52

DV-SL700W
Symbol
M_CS0_B/GPIO
M_BAO
M_DD[15]
M_DD[14]
M_DD[13]
VDD_K2
M_DD[12]
M_DD[11]
M_DD[10]
M_DD[9]
M_DD[8]
M__A[11]/GPIO
VDD_03
M_CLKO
VSS_03/VSS_K3
M_CKE/GPIO
M_A[9]
M_A[8]
M_A[7]
M_A[6]
M_A[5]
VDD_K3
M_A[4]
M_DQM1/GPIO
M_DQM0/GPIO
M_BA1/GPIO
Pin NO I/O
SDRAM chip select 0, or GPIO[24]
100 IO
sft_cfg0[0]=1'b1
sft_cfg8[9]=1'b1
(other)
SDRAM bank select address_[0]_
101 IO
SDRAM data bus [15]
102 IO
SDRAM data bus [14]
103 IO
SDRAM data bus [13]
104 IO
Kernel logic power supply#2
105 S
SDRAM data bus [12]
106 IO
SDRAM data bus [11]
107 IO
SDRAM data bus [10]
108 IO
SDRAM data bus [9]
109 IO
SDRAM data bus [8]
110 IO
SDRAM address bus [11] or GPIO [25]
111 IO
sft_cfg1[4]=1'b1
sft_cfg8[9]=1'b1
(other)
l/O power supply #3
112 S
SDRAM clock output
113 O
Kernel logic/l/O power shared ground supply #3
114 S
SDRAM clock enable, or gpio[26]
115 IO
sft_cfg0[1]=1'b1
sft_cfg8[9]=1'b1
(other)
SDRAM address bus [9]
116 lO
SDRAM address bus [8]
117 lO
SDRAM address bus [7]
118 lO
SDRAM address bus [6]
119 l/O
SDRAM address bus [5]
120 l/O
Kernel logic power supply #3
121 S
SDRAM address bus [4]
122 I/O
SDRAM data input/output mask for M_DD[15:8] or GPIOA[27]
123 I/O
SDRAM data input/output mask for M_DD[7:0] or GPIOA[28]
124 I/O
sft_cfg0[2]
sft_cfg8[8]=1'b1
sft_cfg8[9]=1'b1
(other)
SDRAM bank select address [1] or GPIOA[29]
125 I/O
sft_cfg0[6]=1'b1
sft_cfg8[8]=1'b1
sft_cfg8[9]=1'b1
(other)
Description
Priority selection
Priority selection
Priority selection
Priority selection
Priority selection
52
Function
SDRAM chip
select(default)
DAC_DATA_D[2]
GPIO[24]
Function
DRAM address bus
M_A[11] (default)
DAC_DATA_C[2]
GPIO[25]
Function
DRAM clock enable
(default)
DAC_DATA_C[1]
GPIO[26]
Function
SDRAM data input/output
mask for M_DD[7,8]
(default)
ADC_MONO _D_R[5]
DAC_DATA_B[3]
GPIO[28]
Function
SDRAM bank select
address [1] (default)
ADC_MONO _D_R[6]
DAC_DATA_B[2]
GPIO[29]
Dir
O
I
I/O
Dir
O
I
I/O
Dir
O
I
I/O
Dir
I/O
O
I
I/O
Dir
I/O
O
I
I/O