Sony CDP-LSA1 Service Manual page 46

Pin. No. Pin Name
55 VSS
56 XINT
57 XCS
58 XWR
59 XRD
60 ALE
61 XRDY
62 VDD
63 to 70 A0 to 7
71 VSS
72 INTL/XM16
73 VSS
74 D3
75 D2
76 D1
77 D0
78 VSS
79 CTL1
80 CTL0
81 LREQ
82 VDD
83 SYSCLK
84 VSS
85 XRESET
86 to 94 TS0 to 8
95 VDD
96 HCLKOUT
97 GNCLK
98 TS9
99 DQSY
100 C2PO
101 SBSO
102 EXCK
103 WFCK
104 SCOR
105 TS16
106 TS17
107 TS18
108 VSS
109 VDD
110 A10/TS32
111 A9/TS31
112 A8/TS30
113 A7/TS29
114 A6/TS28
115 A5/TS27
116 VSS
117 A4/TS26
118 A3/TS25
119 A2/TS24
120 A1/TS23
121 A0/TS22
122 XRAS/TS21
46
I/O
— Ground.
O Interrupt signal transmitted to host. (Not used.)
I Chip select signal from host
I Write signal from host
I Read signal from host
I Address latch signal from host (enabled for M16); Fixed at "H" for Intel
O Ready signal transmitted to host (L = Ready)
— Power supply.
I Address bit 0 (when Intel host interface is used)
— Ground.
I Type of host to which connection is to be established. (L = M16; H = Intel)
— Ground.
I/O PHY interface data bus bit 3.
I/O PHY interface data bus bit 2.
I/O PHY interface data bus bit 1.
I/O PHY interface data bus bit 0.
— Ground.
I/O PHY interface control bus bit 1
I/O PHY interface control bus bit 0
O PHY interface request signal
— Power supply.
I PHY interface system clock (49.152 MHz)
— Ground.
I System reset
O Test output. (Not used.)
— Power supply.
O Clock obtained by splitting SYSCLK (24.576 MHz) (Not used.)
O Clock obtained by dividing NCLK in two (6.144 MHz) (Not used.)
O Test output. (Not used.)
O Ubit reception frame pulse (Not used.)
I CD C2 error input.
I CD SubCode data.
O CD SubCode read clock.
I SubCode frame signal.
I CD SubCode frame lead signal.
O "8-bit clock synchronized to 512 fsin (Output at address 30, bit 4 = 1) (Not used.)"
O "L/R clock synchronized to 512 fsin(Output at address 30, bit 4 = 1) (Not used.)"
O DRAM address bit 11. (Not used.)
— Ground.
— Power supply.
O DRAM address bit 10. (Not used.)
O DRAM address bit 9. (Not used.)
O DRAM address bit 8. (Not used.)
O DRAM address bit 7. (Not used.)
O DRAM address bit 6. (Not used.)
O DRAM address bit 5. (Not used.)
— Ground.
O DRAM address bit 4. (Not used.)
O DRAM address bit 3. (Not used.)
O DRAM address bit 2. (Not used.)
O DRAM address bit 1. (Not used.)
O DRAM address bit 0. (Not used.)
O DRAM XRAS. (Not used.)
Function