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4.2.2
Utilizing the MC68EC040 Data Cache
In order to achieve best performance out of the MC68EC040, both caches, Instruction and Data, are used.
Since the bus interface of the EC040 and the QUICC's DMA are different, snooping is not supported on
the M68360QUADS-040. Therefore, when the Data cache is enabled and used, two basic problems arise:
1. When registers or buffer descriptors are changed values by hardware or DMA are to be
polled, they should not be cached, otherwise they will be polled indefinitely from the data
cache, while their value may change outside, unnoticed by application software.
2. Transmit or Receive buffers should not be cached, since they are being used only once,
therefore, not only caching them will not contribute to better performance, but rather will
harm it, since it will keep the replacement mechanism busier.
To answer the above problems, the following measures were taken on the M68360QUADS-040:
1. The QUICC internal memory map area, including the registers and buffer-descriptors
spaces, was moved to the second 16 Mbyte block
in the DTTR1 register of the 68EC040.
2. To allow for memory areas containing Transmit or Receive buffers to avoid being cached,
the Hardware Breakpoint mechanism may be utilized as a caching shield. The BKPTO*
signal of the QUICC is connected via a jumper - J7, to the TCI* signal of the EC040, which
when asserted at the beginning of a data-cache line read cycle, avoids the caching of that
line in the data-cache. As the BKAR and BKCR are programmed to match the address,
size, and attributes of the desired memory space
on the relevant access to that space and avoid redundant caching.
4.3
Interrupts on the M68360QUADS-040
In slave mode (including 68EC040 companion) the QUICC serves as an interrupt encoder for the master
processor. It integrates all internal and external interrupt sources and encodes them to IOUT(0:2)~ to be
connected to standard 68000 IPL~ lines. Since the parity lines are used on the M68360QUADS-040,
IOUT(0:2)~ are used on the expense of IRQ1~, IRQ4~ and IRQ6~ of the slave QUICC.
3
There are 5 external
interrupt sources on the M68360QUADS-040:
1. ABORT push-button - non-maskable, level 7.
2. Host NMI via ADI port - non-maskable, level 7.
3. Hardware-Breakpoint - non-maskable, optional, level 7.
4. Parity error, generated by the slave QUICC's parity logic - maskable, level 5.
5. Host Request / Acknowledge from ADI port - maskable, level 2.
All the level - 7 interrupt source are registered and two of them are available in the status register, this to
allow software to detect the source of the of the interrupt. The interrupts on levels 5 and 2 are most likely
to use the autovector mechanism of the QUICC.
4.3.1
ABORT Push-button
When the ABORT push button - SW2 is depressed, a non-maskable, level-7 interrupt is generated to the
EC040 by the QUICC. When the ABORT push-button is depressed in conjunction with the SOFT-RESET
1. There is no MMU on the MC68EC040, therefore use must be done with one of the two DTTRs - Data Transparent
Translation Registers, of the EC040. These registers can address memory blocks no smaller than 16 MBytes. Since the
first 16 MByte block on board, holds memories that are to be data-cached, the QUICC was moved to the second block.
2. Not bigger than 32K Bytes.
3. Off QUICC.
M68360QUADS-040 Hardware User's Manual
For More Information On This Product,
Go to: www.freescale.com
FUNCTIONAL DESCRIPTION
1
, where it is marked as Non-cashable
2
to be shielded, BKPTO* will be asserted
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