Divider Circuit; When No Subsystem Clock Is Used - NEC UPD789426 Series User Manual

Figure 5-9. Examples of Incorrect Connection for RC Oscillation (3/3)
• Main system clock
CL1 CL2

5.4.5 Divider circuit

The divider circuit divides the output of the main system clock oscillator (f

5.4.6 When no subsystem clock is used

If a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation,
handle the XT1 and XT2 pins as follows:
XT1: Connect to V
SS
XT2: Leave open
In this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator
when the main system clock is stopped. To avoid this, set bit 1 (FRC) of the suboscillation mode register (SCKM) so
that the on-chip feedback resistor will not be used. Also in this case, handle the XT1 and XT2 pins as stated above.
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CHAPTER 5 CLOCK GENERATOR
(e) Signal is fetched
V
SS
User's Manual U15075EJ2V1UD
• Subsystem clock
V
XT1 XT2
SS
, f ) to generate various clocks.
X CC