Functional Description
Table 3-9. 60x Bus to SDRAM Access Timing (100MHz/PC100 SDRAMs)
ACCESS TYPE
3
4-Beat Write after 4-Beat Write,
SDRAM Bank Active - Page Hit
1-Beat Read after idle,
SDRAM Bank Inactive
1-Beat Read after idle,
SDRAM Bank Active - Page Miss
1-Beat Read after idle,
SDRAM Bank Active - Page Hit
1-Beat Read after 1-Beat Read,
SDRAM Bank Active - Page Miss
1-Beat Read after 1-Beat Read,
SDRAM Bank Active - Page Hit
1-Beat Write after idle,
SDRAM Bank Active or Inactive
1-Beat Write after 1-Beat Write,
SDRAM Bank Active - Page Miss
1-Beat Write after 1-Beat Write,
SDRAM Bank Active - Page Hit
3-16
Access Time
(tB1-tB2-tB3-tB4)
3-1-1-1
10
12
7
8
5
5
13
8
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Comments
3-1-1-1 for the second burst
write after idle.
2-1-1-1 for subsequent burst
writes.