Motorola MVME2401-1 Installation And Use Manual
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Motorola MVME2401-1 Installation And Use Manual

Motorola MVME2401-1 Installation And Use Manual

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MVME2400-Series
Single Board Computer
Installation and Use
V2400A/IH1

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  • Page 1 MVME2400-Series Single Board Computer Installation and Use V2400A/IH1...
  • Page 2 While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
  • Page 3 The MVME2400 VME processor module is based on an MPC750 PowerPC microprocessor, and features dual PCI Mezzanine Card (PMC) slots with front panel and/ or P2 I/O. The MVME2400 is currently available in the following configurations: Model Memory Handles MVME2401-1 MPC750 32MB ECC SDRAM Scanbe Handles @ 233 MHz MVME2401-3...
  • Page 4 This manual is intended for anyone who wants to design OEM systems, supply additional capability to an existing compatible system, or work in a lab environment for experimental purposes. A basic knowledge of computers and digital logic is assumed. Document Terminology Throughout this manual, a convention is used which precedes data and address parameters by a character identifying the numeric format as follows: Dollar...
  • Page 5 The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
  • Page 6 Test In accordance with European Community directives, a “Declaration of Conformity” has been made and is on file at Motorola, Inc. - Computer Group, 27 Market Street, Maidenhead, United Kingdom, Sl6 8AE. This board product was tested in a representative system to show compliance with the above mentioned requirements.
  • Page 7 94V-0. The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., 1995, and may be used only under a license such as those contained in Motorola’s software licenses.

  • Page 9: Table Of Contents

    Contents CHAPTER 1 Preparing and Installing the MVME2400-Series Module Introduction........................1-1 MVME240x Description ...................1-1 MVME240x Module...................1-2 PMCspan Expansion Mezzanine ................1-3 PCI Mezzanine Cards (PMCs)................1-3 VMEsystem Enclosure ..................1-4 System Console Terminal ...................1-4 Overview of Start-Up Procedures ................1-4 Unpacking the MVME240x Hardware ..............1-7 Preparing the MVME240x Hardware ................1-7 MVME240x ......................1-7 Setting the Flash Memory Bank A/Bank B Reset Vector Header (J8) ..1-10...
  • Page 10 BFL (DS1)....................2-4 CPU (DS2) ....................2-4 PMC2 (DS3)....................2-4 PMC1 (DS4)....................2-4 10/100 BASET Port.................... 2-4 DEBUG Port....................... 2-5 PMC Slots......................2-7 PCI MEZZANINE CARD (PMC Slot 1)............ 2-7 PCI MEZZANINE CARD (PMC Slot 2)............ 2-7 PMCspan ........................2-8 CHAPTER 3 Functional Description Introduction .......................
  • Page 11 Interrupt Controller (MPIC)................3-28 Programmable Timers..................3-28 Interval Timers ..................3-28 16/32-Bit Timers..................3-29 CHAPTER 4 Programming the MVME240x Introduction........................4-1 Memory Maps ......................4-1 Processor Bus Memory Map................4-2 Default Processor Memory Map..............4-2 PCI Local Bus Memory Map................4-3 VMEbus Memory Map ..................4-3 Programming Considerations..................4-4 PCI Arbitration ....................4-4 Interrupt Handling....................4-6 DMA Channels ....................4-8 Sources of Reset....................4-8...
  • Page 12 APPENDIX A Ordering Related Documentation Motorola Computer Group Documents ..............A-1 Manufacturers’ Documents ..................A-2 Related Specifications ....................A-5 APPENDIX B Specifications Specifications......................B-1 Cooling Requirements ....................B-3 EMC Regulatory Compliance .................. B-4 APPENDIX C Connector Pin Assignments Introduction ......................C-1 Pin Assignments .......................
  • Page 13 List of Figures Figure 1-1. MVME240x Switches, LEDs, Headers, Connectors ......1-9 Figure 1-2. General-Purpose Software-Readable Header........1-11 Figure 1-3. Typical Single-width PMC Module Placement on MVME240x ..1-15 Figure 1-4. PMCspan-002 Installation on an MVME240x ........1-17 Figure 1-5. PMCspan-010 Installation onto a PMCspan-002/MVME240x ....1-19 Figure 2-1.
  • Page 15 Table 4-3. Classes of Reset and Effectiveness ............4-9 Table 5-1. Debugger Commands ................5-7 Table 5-2. Diagnostic Test Groups ................5-12 Table A-1. Motorola Computer Group Documents ..........A-1 Table A-2. Manufacturers’ Documents ..............A-2 Table A-3. Related Specifications ................A-5 Table B-1. MVME240x Specifications ..............B-1 Table C-1.

  • Page 17: Introduction

    1Preparing and Installing the MVME2400-Series Module Introduction This chapter provides a brief description of the MVME2400-Series VME Processor Module, and instructions for preparing and installing the hardware. In this manual, the name MVME240x refers to all models of the MVME2400-series boards, unless otherwise specified. MVME240x Description The MVME2400-series VME processor module is a PCI Mezzanine Card (PMC) carrier board.

  • Page 18: Mvme240X Module

    PMCs. It occupies a single VMEmodule slot, except when optional PCI expansion mezzanine modules are also used: Table 1-1. MVME240x Models Model Memory Handles MVME2401-1 MPC750 32MB ECC SDRAM Scanbe Handles @ 233 MHz MVME2401-3 32MB ECC SDRAM...

  • Page 19: Pmcspan Expansion Mezzanine

    MVME240x Description Support for two IEEE P1386.1 PCI mezzanine cards is provided via eight 64-pin SMT connectors. Front panel openings are provided on the MVME240x board for the two PMC slots. In addition, there are 64 pins of I/O from PMC slot 1 and 46 pins of I/O from PMC slot 2 that are routed to P2.

  • Page 20: Vmesystem Enclosure

    Preparing and Installing the MVME2400-Series Module The MVME240x board supports both front panel I/O and rear panel P2 I/O through either PMC slot 1 or PMC slot 2. 64 pins of I/O from slot 1 and 46 pins of I/O from slot 2 are routed directly to P2. VMEsystem Enclosure Your MVME240x board must be installed in a VMEsystem chassis with both P1 and P2 backplane connections.
  • Page 21 Overview of Start-Up Procedures Table 1-3. Start-Up Overview (Continued) What you need to do ... Refer to ... On page ... Prepare the PMCspan module(s). PMCspan 1-12 For additional information on PMCspan, refer to the PMCspan PMC Adapter Carrier Module Installation and Use manual, listed in Appendix A, Ordering Related Documentation.
  • Page 22 Preparing and Installing the MVME2400-Series Module Table 1-3. Start-Up Overview (Continued) What you need to do ... Refer to ... On page ... Connect any other optional Connector Pin Assignments devices or equipment you will be For more information on optional devices using.

  • Page 23: Unpacking The Mvme240X Hardware

    The MVME240x control registers are briefly described in Chapter 4, with additional information in the MVME2400- Series VME Processor Module Programmer’s Reference Guide as listed in the table Motorola Computer Group Documents in Appendix A, Ordering Related Documents. http://www.mcg.mot.com/literature...
  • Page 24 Preparing and Installing the MVME2400-Series Module Some options, however, are not software-programmable. Such options are controlled through manual installation or removal of header jumpers or interface modules on the MVME240x or the associated modules. Figure 1-1 illustrates the placement of the switches, jumper headers, connectors, and LED indicators on the MVME240x.

  • Page 25: Mvme240X

    Preparing the MVME240x Hardware MVME 240X 1 2 3 4 5 6 7 8 Figure 1-1. MVME240x Switches, LEDs, Headers, Connectors http://www.mcg.mot.com/literature...

  • Page 26: Setting The Flash Memory Bank A/Bank B Reset Vector Header (J8)

    Preparing and Installing the MVME2400-Series Module Setting the Flash Memory Bank A/Bank B Reset Vector Header (J8) Bank B consists of 1 MB of 8-bit Flash memory in two 32-pin PLCC 8-bit sockets. Bank A consists of four 16-bit devices that are populated with 16Mbit Flash devices (8 MB).

  • Page 27: Setting The General-Purpose Software-Readable Header (Srh) Switch(S3)

    SRH Register Bit 7 is associated with Pin 8 and Pin 9 of the SRH. The SRH is a read-only register. If Motorola’s PowerPC firmware, PPCBug, is being used, it reserves all bits, SRH0 to SRH7. If it is not being used, the switch can be used for other applications.

  • Page 28: Pmcs

    Preparing and Installing the MVME2400-Series Module PMCs For a discussion of any configurable items on the PMCs, refer to the user’s manual for the particular PMCs. PMCspan You will need to use an additional slot in the VME chassis for each PMCspan expansion module you plan to use.

  • Page 29: Installing The Mvme240X Hardware

    MVME240x into a VME chassis, and connecting an optional system console terminal. ESD Precautions Motorola strongly recommends that you use an antistatic wrist strap and a conductive foam pad when installing or upgrading a system. Electronic components, such as disk drives, computer boards, and memory modules, can be extremely sensitive to Electro-Static Discharge (ESD).
  • Page 30 Preparing and Installing the MVME2400-Series Module Inserting or removing modules with power applied may result in damage to module components. Caution Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting. Warning 3.

  • Page 31: Figure 1-3. Typical Single-Width Pmc Module Placement On Mvme240X

    Installing the MVME240x Hardware 2064 9708 Figure 1-3. Typical Single-width PMC Module Placement on MVME240x 5. Slide the edge connector(s) of the PMC module into the front panel opening(s) from behind and place the PMC module on top of the MVME240x.

  • Page 32: Primary Pmcspan

    Preparing and Installing the MVME2400-Series Module Primary PMCspan To install a PMCspan-002 PCI expansion module on your MVME240x, refer to Figure 1-4 and perform the following steps. This procedure assumes that you have read the user’s manual that was furnished with the PMCspan, and that you have installed the selected PMCs on the PMCspan according to the instructions given in the PMCspan and PMC manuals.

  • Page 33: Figure 1-4. Pmcspan-002 Installation On An Mvme240X

    Installing the MVME240x Hardware 2081 9708 Figure 1-4. PMCspan-002 Installation on an MVME240x http://www.mcg.mot.com/literature 1-17...

  • Page 34: Secondary Pmcspan

    Preparing and Installing the MVME2400-Series Module 4. Attach the four standoffs to the MVME240x module. For each standoff: – Insert the threaded end into the standoff hole at each corner of the VME processor module. – Thread the locking nuts onto the standoff tips. –...

  • Page 35: Figure 1-5. Pmcspan-010 Installation Onto A Pmcspan-002/Mvme240X

    Installing the MVME240x Hardware 2065 9708 Figure 1-5. PMCspan-010 Installation onto a PMCspan-002/MVME240x http://www.mcg.mot.com/literature 1-19...
  • Page 36 Preparing and Installing the MVME2400-Series Module 2. Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the VME module card cage.

  • Page 37: Mvme240X

    Installing the MVME240x Hardware MVME240 x Before installing the MVME240x into your VME chassis, ensure that the jumpers on the MVME240x J8, J9, and S3 switch are configured, as previously described. This procedure assumes that you have already installed the PMCspan(s) if desired, and any PMCs that you have selected. Proceed as follows to install the MVME240x in the VME chassis: 1.
  • Page 38 RF emissions. Note Some VME backplanes (e.g., those used in Motorola “Modular Chassis” systems) have an auto-jumpering feature for automatic propagation of the IACK and BG signals. Step 6 does not apply to such backplane designs.

  • Page 39: Installation Considerations

    Installing the MVME240x Hardware 8. Replace the chassis or system cover(s), cable peripherals to the panel connectors as appropriate, reconnect the system to the AC or DC power source, and turn the equipment power on. 9. The MVME240x’s green LED indicates activity as a set of confidence tests is run, and the debugger prompt PPC1-Bug>...
  • Page 40 Preparing and Installing the MVME2400-Series Module Other MPUs on the VMEbus can interrupt, disable, communicate with, and determine the operational status of the processor(s). One register of the Universe set includes four bits that function as location monitors to allow one MVME240x processor to broadcast a signal to any other MVME240x processors.

  • Page 41: Introduction

    2Operating Instructions Introduction This chapter provides information about powering up the MVME240x system, and functionality of the switches, status indicators, and I/O ports on the front panels of the MVME240x and PMCspan modules. Applying Power After you have verified that all necessary hardware preparation has been done, that all connections have been made correctly, and that the installation is complete, you can power up the system.

  • Page 42: Mvme240X

    Operating Instructions Power-up/reset initialization STARTUP Initialize devices on the MVME240x INITIALIZATION module/system Power On Self Test diagnostics POST Firmware-configured boot mechanism, BOOTING if so configured. Default is no boot. Interactive, command-driven on-line PowerPC MONITOR debugger, when terminal connected. MVME240 x The front panel of the MVME240x module is shown on a following page.

  • Page 43: Abt (S1)

    MVME240x ABT (S1) When activated by software, the Abort switch, , can generate an interrupt signal from the base board to the processor at a user- programmable level. The interrupt is normally used to abort program execution and return control to the debugger firmware located in the MVME240x Flash memory.

  • Page 44: Status Indicators

    Operating Instructions Status Indicators MVME There are four LED (light-emitting diode) status 240x indicators located on the MVME240x front panel.: BFL, , and PMC2 PMC1 BFL (DS1) The yellow LED indicates board failure; lights when the BRDFAIL* signal line is active. CPU (DS2) The green LED indicates CPU activity;...

  • Page 45: Debug Port

    MVME240x DEBUG Port The RJ45 port labeled on the front panel of the MVME240x DEBUG supplies the MVME240x serial communications interface, implemented via a UART PC16550 controller chip from National Semiconductor. It is asynchronous only. This serial port is configured for EIA-232-D DTE, as shown in Figure 2-1.

  • Page 46: Figure 2-1. Mvme240X Debug Port Configuration

    Operating Instructions SOUT RTS* DTR* CTS* DCD* PC16550 Debug MVME240x RJ45 Figure 2-1. MVME240x DEBUG Port Configuration Computer Group Literature Center Web Site...

  • Page 47: Pmc Slots

    MVME240x PMC Slots Two openings located on the front panel provide I/O expansion by allowing access to one or two 4-port single- wide or one 8-port double-wide PCI Mezzanine Card (PMC), connected to the PMC connectors on the MVME240x. For pin assignments for the PMC connectors, refer to Appendix C.

  • Page 48: Pmcspan

    Operating Instructions PMCspan A PMCspan front panel is pictured on the previous page. The front panel is the same for all PMCspan models. There are two PMC slots, labeled , which support PCI MEZZANINE CARD either two single-wide PMCs or one double-wide PMC. The PMCspan board has two sets of three 32-bit connectors for PMC interface to a secondary PCI bus and a user-specific I/O.

  • Page 49: Introduction

    3Functional Description Introduction This chapter describes the MVME240x VME processor module on a block diagram level. The General Description provides an overview of the MVME240x, followed by a detailed description of several blocks of circuitry. Figure 3-1 shows a block diagram of the overall board architecture.
  • Page 50 Functional Description Table 3-1. MVME240x Features (Continued) Feature Description Sockets for 1 MB Flash memory 8 MB Soldered on-board Memory Controller Hawk’s SMC (System Memory Controller) PCI Host Bridge Hawk’s PHB (PCI Host Bridge) Interrupt Controller Hawk’s MPIC (Multi-Processor Interrupt Controller) PCI Interface 32/64-bit Data, 33MHz operation 8KB NVRAM with RTC and battery backup (SGS-Thomson...
  • Page 51 Features Table 3-1. MVME240x Features (Continued) Feature Description VMEbus system controller functions 64-bit PCI (Universe 2) VMEbus-to-local-bus interface (A32/A24/A16, D64 (MBLT) D32//D16/D08 Master and Slave Local-bus-to-VMEbus interface (A16/A24/A32, D8/D16/D32) VMEbus interface VMEbus interrupter VMEbus interrupt handler Global Control/Status Register (GCSR) for interprocessor communications DMA for fast local memory/VMEbus transfers (A16/A24/A32, D16/D32/D64)

  • Page 52: General Description

    Functional Description General Description The MVME240x is a VME processor module equipped with a PowerPC 604 RISC (MPC750) microprocessor. As shown in the Features section, the MVME240x offers many standard features desirable in a computer system—including Ethernet and debug ports, Boot ROM, Flash memory, SDRAM, and interface for two PCI Mezzanine Cards (PMCs), contained in a one-slot VME package.

  • Page 53: Figure 3-1. Mvme240X Block Diagram

    Block Diagram Debug Connector SDRAM 32/64/128MB L2 Cache 512KB FLASH or 1M 1MB to 9MB System Registers Processor MPC750 Hawk ASIC Clock System Memory Controller (SMC) Generator and PCI Host Bridge (PHB) 33MHz 32/64-bit PCI Local Bus Ethernet VME Bridge W83c553 Universe DEC21143...

  • Page 54: L2 Cache

    Functional Description The PowerPC 750 is a 64-bit processor with 32 KB on-chip caches (32KB data cache and 32KB instruction cache). The PHB bridge controller portion of the Hawk ASIC provides the bridge between the PowerPC microprocessor bus and the PCI local bus. Electrically, the Hawk is a 64-bit PCI connection.

  • Page 55: Hawk System Memory Controller (Smc)/Pci Host Bridge (Phb) Asic

    Block Diagram Hawk System Memory Controller (SMC)/PCI Host Bridge (PHB) ASIC The Hawk ASIC provides the bridge function between the MPC60x bus and the PCI Local Bus. It provides 32-bit addressing and 64-bit data. The 64-bit addressing (dual address cycle) is not supported. The Hawk supports various PowerPC processor external bus frequencies up to 100MHz.

  • Page 56: Pci Bus Latency

    Functional Description PCI Bus Latency The following table lists the latency of PCI originated transactions for five different clock ratios: 5:2, 3:2, 3:1, 2:1, and 1:1. The MVME2400 uses a 3:1 clock ratio: Table 3-3. PCI Originated Latency Matrix 32-bit PCI 64-bit PCI Clock Transaction...
  • Page 57 Block Diagram Table 3-4. PCI Originated Bandwidth Matrix First 2 First 4 First 6 Continuous Cache Lines Cache Lines Cache Lines Clock Transaction Ratio MBytes MBytes MBytes Clks/ MBytes Clks Clks Clks Line 64-bit Writes 64-bit Reads 32-bit Writes 32-bit Reads 64-bit Writes 64-bit Reads 32-bit Writes...

  • Page 58: Ppc Bus Latency

    Functional Description PPC Bus Latency The following tables list the latency of PPC originated transactions and the bandwidth of originated transactions for five different clock ratios: 5:2, 3:2, 3:1, 2:1, and 1:1. The MVME2400 uses a 3:1 clock ratio: Table 3-5. PPC60x Originated Latency Matrix 32-bit PCI 64-bit PCI Clock...
  • Page 59 Block Diagram Table 3-6. PPC60x Originated Bandwidth Matrix First 2 First 4 First 6 Continuous Cache Lines Cache Lines Cache Lines Clock Transaction Ratio MBytes MBytes MBytes Clks/ MBytes Clks Clks Clks Line 64-bit Writes 64-bit Reads 32.5 32-bit Writes 32-bit Reads 42.5 64-bit Writes...

  • Page 60: Assumptions

    Functional Description Table 3-7. PCI Originated Bandwidth Matrix First 2 First 4 First 6 Continuous Cache Lines Cache Lines Cache Lines Clock Transaction Ratio MBytes MBytes MBytes Clks/ MBytes Clks Clks Clks Line 64-bit Writes 64-bit Reads 32-bit Writes 32-bit Reads 64-bit Writes 64-bit Reads 32-bit Writes...

  • Page 61: Clock Ratios And Operating Frequencies

    Block Diagram Clock Ratios and Operating Frequencies Performance is based on the appropriate clock ratio and corresponding operating frequency:’ Table 3-8. Clock Ratios and Operating Frequencies PPC60x Clock PCI Clock SDRAM Speed Ratio (MHz) (MHz) (ns) PPC60x Originated Count represents number of PPC60x bus clock cycles. Assumes write posting FIFO is initially empty.

  • Page 62: Pci Originated

    Functional Description Clock counts represent best case alignment between PCI and PPC60x clock domains. An exception to this is continuous bandwidth which reflects the average affects of clock alignment. PCI Originated Count represents number of PCI Bus clock cycles. Assumes write posting FIFO is initially empty L2 caching is not enabled, all transactions exclusively controlled by the SMC.

  • Page 63: Sdram Latency

    Block Diagram consisting of 18 devices that total 128Mbytes. With 128Mbit (4bit data) devices, the block contains 256Mbytes. When populated, these blocks appear as Block A and Block B to the Hawk. Refer to the MVME2400-Series VME Processor Module Programmer’s Reference Guide for additional information and programming details.
  • Page 64 Functional Description Table 3-9. 60x Bus to SDRAM Access Timing (100MHz/PC100 SDRAMs) Access Time ACCESS TYPE Comments (tB1-tB2-tB3-tB4) 4-Beat Write after 4-Beat Write, 3-1-1-1 3-1-1-1 for the second burst write after idle. SDRAM Bank Active - Page Hit 2-1-1-1 for subsequent burst writes.
  • Page 65 Block Diagram Notes 1. SDRAM speed attributes are programmed for the following: CAS_latency = 2, tRCD = 2 CLK Periods, tRP = 2 CLK Periods, tRAS = 5 CLK Periods, tRC = 7 CLK Periods, tDP = 2 CLK Periods, and the swr_dpl bit is set in the SDRAM Speed Attributes Register.
  • Page 66 Functional Description Notes When the initial bus state is idle, tB1 reflects the number of CLK periods from the rising edge of the CLK that drives TS_low, to the rising edge of the CLK that samples the first TA_low. When the bus is busy and TS_ is being asserted as soon as possible after Hawk asserts AACK_ the back-to-back condition occurs.

  • Page 67: Flash Memory

    Block Diagram Flash Memory The MVME240x base board contains two banks of FLASH memory. Bank B consists of two 32-pin devices which can be populated with 1MB of FLASH memory. Only 8-bit writes are supported for this bank. Bank A has four 16-bit Smart Voltage FLASH SMT devices.
  • Page 68 Functional Description Table 3-10. PPC Bus to ROM/Flash Access Timing (120ns @ 100MHz) CLOCK PERIODS REQUIRED FOR: Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat ACCESS TYPE Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 4-Beat Read 4-Beat Write 1-Beat Read (1 byte) 1-Beat Read (2 to 8 bytes)
  • Page 69 Block Diagram Table 3-12. PPC Bus to ROM/Flash Access Timing (50ns @ 100MHz) CLOCK PERIODS REQUIRED FOR: Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat ACCESS TYPE Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 4-Beat Read 4-Beat Write 1-Beat Read (1 byte) 1-Beat Read (2 to 8 bytes)

  • Page 70: Ethernet Interface

    Functional Description Ethernet Interface The MVME240x module uses Digital Equipment’s DECchip 21143 PCI Fast Ethernet LAN controller to implement an Ethernet interface that supports 10Base-T/100Base-TX connections, via an RJ45 connector on the front panel. The balanced differential transceiver lines are coupled via on-board transformers.

  • Page 71: Pci Mezzanine Card (Pmc) Interface

    Block Diagram PCI Mezzanine Card (PMC) Interface A key feature of the MVME240x family is the PCI bus. In addition to the on-board local bus devices (Ethernet, etc.), the PCI bus supports an industry-standard mezzanine interface, IEEE P1386.1 PCI Mezzanine Card (PMC).

  • Page 72: Pmc Slot 2 (Single-Width Pmc)

    Functional Description For P2 I/O configurations, all I/O pins of PMC slot 1 are routed to the 5- row power adapter card. Pins 1 through 64 of J14 are routed to row C and row A of P2. PMC Slot 2 (Single-Width PMC) PMC slot 2 has the following characteristics: Mezzanine Type PCI Mezzanine Card (PMC)

  • Page 73: Vmebus Interface

    Block Diagram VMEbus Interface The VMEbus interface is implemented with the CA91C142 Universe ASIC. The Universe chip interfaces the 32/64-bit PCI local bus to the VMEbus. The Universe ASIC provides: The PCI-bus-to-VMEbus interface The VMEbus-to-PCI-bus interface The DMA controller functions of the local VMEbus The Universe chip includes Universe Control and Status Registers (UCSRs) for interprocessor communications.

  • Page 74: Pci-Isa Bridge (Pib) Controller

    Functional Description For detailed programming information, refer to the MVME2400-Series VME Processor Module Programmer’s Reference Guide and to Texas Instrument’s data sheet #SLLS057D, dated August 1989, revised March 1996 for Asynchronous Communications Element (ACE) TL16C550A. PCI-ISA Bridge (PIB) Controller The MVME240x uses a Winbond W83C553 PCI/ISA Bridge (PIB) Controller to supply the interface between the PCI local bus and the ISA system I/O bus (diagrammed in Figure 3-1).

  • Page 75: Real-Time Clock/Nvram/Timer Function

    Block Diagram Real-Time Clock/NVRAM/Timer Function The MVME240x employs an SGS-Thomson surface-mount M48T559 RAM and clock chip to provide 8KB of non-volatile static RAM, a real- time clock, and a watchdog timer function. This chip supplies a clock, oscillator, crystal, power failure detection, memory write protection, 8KB of NVRAM, and a battery in a package consisting of two parts: A 28-pin 330mil SO device containing the real-time clock, the oscillator, power failure detection circuitry, timer logic, 8KB of...

  • Page 76: Interrupt Controller (Mpic)

    Functional Description Interrupt Controller (MPIC) The MPIC Interrupt Controller portion of the Hawk ASIC is designed to handle various interrupt sources. The interrupt sources are: Four MPIC timer interrupts Processor 0 self interrupt Memory Error interrupt from the SMC Interrupts from all PCI devices Two software interrupts ISA interrupts (actually handles as a single 8259 interrupt at INT0) Programmable Timers...

  • Page 77: 16/32-Bit Timers

    Block Diagram The interval timers use the OSC clock input as their clock source. The MVME240x drives the OSC pin with a 14.31818MHz clock source. 16/32-Bit Timers There is one 16-bit timer and four 32-bit timers on the MVME240x. The 16-bit timer is provided by the PIB.
  • Page 78 Functional Description 3-30 Computer Group Literature Center Web Site...

  • Page 79: Introduction

    4Programming the MVME240x Introduction This chapter provides basic information useful in programming the MVME240x. This includes a description of memory maps, control and status registers, PCI arbitration, interrupt handling, sources of reset, and big/little endian issues. For additional programming information about the MVME240x, refer to the MVME2400-Series VME Processor Module Programmer’s Reference Guide.

  • Page 80: Processor Bus Memory Map

    Programming the MVME240x Processor Bus Memory Map The processor memory map configuration is under the control of the PHB and SMC portions of the Hawk ASIC. The Hawk adjusts system mapping to suit a given application via programmable map decoder registers. At system power-up or reset, a default processor memory map takes over.

  • Page 81: Pci Local Bus Memory Map

    Memory Maps For detailed processor memory maps, including suggested CHRP- and PREP-compatible memory maps, refer to the MVME2400-Series VME Processor Module Programmer’s Reference Guide. PCI Local Bus Memory Map The PCI memory map is controlled by the MPU/PCI bus bridge controller portion of the Hawk ASIC and by the Universe PCI/VME bus bridge ASIC.

  • Page 82: Programming Considerations

    Programming the MVME240x Programming Considerations Good programming practice dictates that only one MPU at a time have control of the MVME240x control registers. Of particular note are: Registers that modify the address map Registers that require two cycles to access VMEbus interrupt request registers PCI Arbitration There are seven potential PCI bus masters on the MVME240x :...

  • Page 83: Figure 4-1. Vmebus Master Mapping

    Programming Considerations VMEBUS PROCESSOR PCI MEMORY ONBOARD MEMORY PROGRAMMABLE SPACE NOTE 2 NOTE 1 PCI MEMORY SPACE VME A24 VME A16 NOTE 3 VME A24 VME A16 NOTE 1 VME A24 PCI/ISA MEMORY SPACE VME A16 VME A24 I/O SPACE VME A16 RESOURCES NOTES:...

  • Page 84: Interrupt Handling

    Programming the MVME240x The arbitration assignments for the MVME240x are shown in Table 4-2. Table 4-2. PCI Arbitration Assignments PCI Bus Request PCI Master(s) PIB (Internal) Hawk ASIC Request 0 PMC Slot 2 Request 1 PMC Slot 1 Request 2 PCI Expansion Slot Request 3 Ethernet...

  • Page 85: Figure 4-2. Mvme240X Interrupt Architecture

    Programming Considerations INT_ Processor (8529 Pair) MCP_ Hawk MPIC SERR_& PERR_ PCI Interrupts ISA Interrupts 11559.00 9609 Figure 4-2. MVME240x Interrupt Architecture The MVME240x routes the interrupts from the PMCs and PCI expansion slots as follows: http://www.mcg.mot.com/literature...

  • Page 86: Dma Channels

    Programming the MVME240x PMC Slot 1 PMC Slot 2 PCIX Slot INTA# INTB# INTC# INTD# INTA# INTB# INTC# INTD# INTA# INTB# INTC# INTD# IRQ9 IRQ10 IRQ11 IRQ12 Hawk MPIC DMA Channels The PIB supports seven DMA channels. They are not functional on the MVME240x.

  • Page 87: Table 4-3. Classes Of Reset And Effectiveness

    Programming Considerations 7. VMEbus Reset sources from the Universe ASIC (PCI/VME bus bridge controller): the System Software reset, Local Software Reset, and VME CSR Reset functions Table 4-3 shows which devices are affected by the various types of resets. For details on using resets, refer to the MVME2400-Series VME Processor Module Programmer’s Reference Guide.

  • Page 88: Endian Issues

    Programming the MVME240x Endian Issues The MVME240x supports both little-endian (e.g., Windows NT) and big- endian (e.g., AIX) software. The PowerPC processor and the VMEbus are inherently big-endian, while the PCI bus is inherently little-endian. The following sections summarize how the MVME240x handles software and hardware differences in big- and little-endian operations.

  • Page 89: Vmebus Domain

    Programming Considerations endian mode, no endian issues should arise for Ethernet data. Big-endian software must still take the byte-swapping effect into account when accessing the registers of the PCI/Ethernet device, however. Role of the Universe ASIC Because the PCI bus is little-endian while the VMEbus is big-endian, the Universe PCI/VME bus bridge ASIC performs byte swapping in both directions (from PCI to VMEbus and from VMEbus to PCI) to maintain address invariance, regardless of the mode of operation in the processor’s...
  • Page 90 Programming the MVME240x 4-12 Computer Group Literature Center Web Site...

  • Page 91: Ppcbug Overview

    Related Documentation appendix. PPCBug Basics The PowerPC debug firmware, PPCBug, is a powerful evaluation and debugging tool for systems built around the Motorola PowerPC microcomputers. Facilities are available for loading and executing user programs under complete operator control for system evaluation.
  • Page 92 PPCBug Breakpoint and tracing capabilities A powerful assembler and disassembler useful for patching programs A self-test at power-up feature which verifies the integrity of the system PPCBug consists of three parts: A command-driven, user-interactive software debugger, described in the PPCBug Firmware Package User’s Manual. It is hereafter referred to as “the debugger”...

  • Page 93: Memory Requirements

    MPU, Hardware, and Firmware Initialization Memory Requirements PPCBug requires a maximum of 768KB of read/write memory (i.e., DRAM). The debugger allocates this space from the top of memory. For example, a system containing 64MB ($04000000) of read/write memory will place the PPCBug memory page at locations $03F40000 to $03FFFFFF.
  • Page 94 PPCBug 7. Calculates the external bus clock speed of the MPU. 8. Delays for 750 milliseconds. 9. Determines the CPU base board type. 10. Sizes the local read/write memory (i.e., DRAM). 11. Initializes the read/write memory controller. Sets base address of memory to $00000000.

  • Page 95: Using Ppcbug

    Using PPCBug 27. Calculates and displays the MPU clock speed, verifies that the MPU clock speed matches the configuration data, and displays a warning message if the verification fails. 28. Displays the BUS clock speed, verifies that the BUS clock speed matches the configuration data, and displays a warning message if the verification fails.

  • Page 96: Debugger Commands

    PPCBug been specified, then control returns to the debugger when the breakpoint is encountered during execution of the user program. Alternately, the user program could return to the debugger by means of the System Call Handler routine RETURN (described in the PPCBug Firmware Package User’s Manual, Chapter 5).

  • Page 97: Table 5-1. Debugger Commands

    Using PPCBug Table 5-1. Debugger Commands Command Description One Line Assembler Block of Memory Compare Block of Memory Fill Block of Memory Initialize Block of Memory Move Breakpoint Insert NOBR Breakpoint Delete Block of Memory Search Block of Memory Verify CACHE Modify Cache State Concurrent Mode...
  • Page 98 PPCBug Table 5-1. Debugger Commands (Continued) Command Description GEVEDIT Global Environment Variable Edit GEVINIT Global Environment Variable Initialization GEVSHOW Global Environment Variable(s) Display Go to Next Instruction G, GO Go Execute User Program Go to Temporary Breakpoint Help IDLE Idle Master MPU I/O Control for Disk I/O Inquiry I/O Physical (Direct Disk Access)
  • Page 99 Using PPCBug Table 5-1. Debugger Commands (Continued) Command Description Memory Set Memory Write Automatic Network Boot Nap MPU Network Boot Operating System, Halt Network Boot Operating System NIOC Network I/O Control NIOP Network I/O Physical NIOT Network I/O Teach (Configuration) NPING Network Ping Offset Registers Display/Modify...

  • Page 100: Diagnostic Tests

    PPCBug Table 5-1. Debugger Commands (Continued) Command Description Switch Directories Set Time and Date SROM SROM Examine/Modify Symbol Table Attach NOSYM Symbol Table Detach SYMS Symbol Table Display/Search Trace Terminal Attach TIME Display Time and Date Transparent Mode Trace to Temporary Breakpoint Verify S-Records Against Memory Revision/Version Display Write Loop...
  • Page 101 Using PPCBug If you are in the debugger directory, the debugger prompt PPC4-Bug> displays, and all of the debugger commands are available. Diagnostics commands cannot be entered at the prompt. PPC4-Bug> If you are in the diagnostic directory, the diagnostic prompt PPC4-Diag>...

  • Page 102: Table 5-2. Diagnostic Test Groups

    PPCBug Table 5-2. Diagnostic Test Groups Test Group Description CL1283 Parallel Interface (CL1283) Tests* DEC21x43 Ethernet Controller Tests HAWK HAWK Tests ISABRDGE PCI/ISA Bridge Tests KBD8730x PC8730x Keyboard/Mouse Tests* L2CACHE Level 2 Cache Tests NCR 53C8xx SCSI-2 I/O Processor Tests PAR8730x Parallel Interface (PC8730x) Test* UART...

  • Page 103: Overview

    6Modifying the Environment Overview You can use the factory-installed debug monitor, PPCBug, to modify certain parameters contained in the MVME240x’s Non-Volatile RAM (NVRAM), also known as Battery Backed-up RAM (BBRAM). The Board Information Block in NVRAM contains various elements concerning operating parameters of the hardware. Use the PPCBug command CNFG to change those parameters.

  • Page 104: Cnfg - Configure Board Information Block

    System Serial Number = “ nnnnnnn ” System Identifier = “Motorola MVME2400” = “ nnnnnnnn “ License Identifier The parameters that are quoted are left-justified character (ASCII) strings padded with space characters, and the quotes (“) are displayed to indicate the size of the string.

  • Page 105: Env - Set Environment

    ENV - Set Environment ENV - Set Environment Use the ENV command to view and/or configure interactively all PPCBug operational parameters that are kept in Non-Volatile RAM (NVRAM). Refer to the PPCBug Firmware Package User’s Manual for a description of the use of ENV. Additional information on registers in the Universe ASIC that affect these parameters is contained in your MVME2400-Series VME Processor Module Programmer’s Reference Guide.
  • Page 106 Modifying the Environment Remote Start Method Switch [G/M/B/N] = B? The Remote Start Method Switch is used when the MVME2400 is cross-loaded from another VME-based CPU, to start execution of the cross-loaded program. Use the Global Control and Status Register to pass and start execution of the cross-loaded program.
  • Page 107 ENV - Set Environment Network PReP-Boot Mode Enable [Y/N] = N? Enable PReP-style network booting (same boot image from a network interface as from a mass storage device). Do not enable PReP-style network booting. (Default) Negate VMEbus SYSFAIL* Always [Y/N] = N? ∗...
  • Page 108 Modifying the Environment NVRAM Bootlist (GEV.fw-boot-path) Boot Enable [Y/N] = N? Give boot priority to devices defined in the fw-boot- path global environment variable (GEV). Do not give boot priority to devices listed in the fw- boot-path GEV. (Default) Note When enabled, the GEV (Global Environment Variable) boot takes priority over all other boots, including Autoboot and Network Boot.
  • Page 109 ENV - Set Environment Auto Boot Scan Enable [Y/N] = Y? If Autoboot is enabled, the Autoboot process attempts to boot from devices specified in the scan list (e.g., ). (Default) FDISK/CDROM/TAPE/HDISK If Autoboot is enabled, the Autoboot process uses the Controller LUN and Device LUN to boot.
  • Page 110 Modifying the Environment You may specify a string (filename) which is passed on to the code being booted. The maximum length of this string is 16 characters. (Default = null string) ROM Boot Enable [Y/N] = N? The ROMboot function is enabled. The ROMboot function is disabled.
  • Page 111 ENV - Set Environment Network Auto Boot Enable [Y/N] = N? The Network Auto Boot (NETboot) function is enabled. The NETboot function is disabled. (Default) Network Auto Boot at power-up only [Y/N] = N? NETboot is attempted at power-up reset only. NETboot is attempted at any reset.
  • Page 112 Modifying the Environment If you use the NIOT debugger command, these parameters need to be saved somewhere in the offset range $00001000 through $000016F7. The NIOT parameters do not exceed 128 bytes in Caution size. The setting of this ENV pointer determines their location. If you have used the same space for your own program information or commands, they will be overwritten and lost.
  • Page 113 ENV - Set Environment ROMFAL setting is $00; the highest allowable is $1F. The value to enter depends on processor speed; refer to Chapter 1 or Appendix B for appropriate values. The default value varies according to the system’s bus clock speed. Note ROM First Access Length is not applicable to the MVME2400.

  • Page 114: Configuring The Vmebus Interface

    Modifying the Environment Initializes the PIRQx (PCI Interrupts) route control registers in the IBC (PCI/ISA bus bridge controller). The ENV parameter is a 32-bit value that is divided by 4 to yield the values for route control registers PIRQ0/1/2/3. The default is determined by system type. For details on PCI/ISA interrupt assignments and for suggested values to enter for this parameter, refer to the 8259 Interrupts section of Chapter 5 in the MVME2400-Series VME Processor Module Programmer’s Reference...
  • Page 115 ENV - Set Environment PCI Slave Image 0 Control = 00000000? The configured value is written into the LSI0_CTL register of the Universe chip. PCI Slave Image 0 Base Address Register = 00000000? The configured value is written into the LSI0_BS register of the Universe chip.
  • Page 116 Modifying the Environment PCI Slave Image 2 Bound Address Register = 22000000? The configured value is written into the LSI2_BD register of the Universe chip. PCI Slave Image 2 Translation Offset = D0000000? The configured value is written into the LSI2_TO register of the Universe chip.
  • Page 117 ENV - Set Environment The configured value is written into the VSI1_CTL register of the Universe chip. VMEbus Slave Image 1 Base Address Register = 00000000? The configured value is written into the VSI1_BS register of the Universe chip. VMEbus Slave Image 1 Bound Address Register = 00000000? The configured value is written into the VSI1_BD register of the Universe chip.
  • Page 118 Modifying the Environment VMEbus Slave Image 3 Translation Offset = 00000000? The configured value is written into the VSI3_TO register of the Universe chip. PCI Miscellaneous Register = 10000000? The configured value is written into the LMISC register of the Universe chip.

  • Page 119: Appendix A Ordering Related Documentation

    The publications listed below are on related products, and some may be referenced in this document. If not shipped with this product, manuals may be purchased by contacting your local Motorola sales office. Table A-1. Motorola Computer Group Documents Publication...

  • Page 120: Manufacturers' Documents

    Table A-2. Manufacturers’ Documents Publication Document Title and Source Number PowerPC 750 RISC Microprocessor Technical Summary MPC750/D Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 E-mail: ldcformotorola@hibbertco.com PowerPC 750 RISC Microprocessor User’s Manual MPC750UM/AD...
  • Page 121 Table A-2. Manufacturers’ Documents (Continued) Publication Document Title and Source Number PowerPC Microprocessor Family: The Programming Environments MPCFPE/AD Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 E-mail: ldcformotorola@hibbertco.com IBM Microelectronics Mail Stop A25/862-1 MPRPPCFPE-01...
  • Page 122 Manufacturers’ Documents Table A-2. Manufacturers’ Documents (Continued) Publication Document Title and Source Number W83C553 Enhanced System I/O Controller with PCI Arbiter (PIB) W83C553 Winbond Electronics Corporation Winbond Systems Laboratory 2730 Orchard Parkway San Jose, CA 95134 Telephone: (408) 943-6666 FAX:(408) 943-6668 M48T559 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet M48T59...

  • Page 123: Related Specifications

    Ordering Related Documentation Related Specifications For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is also provided. Please note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice.
  • Page 124 Related Specifications Table A-3. Related Specifications (Continued) Publication Document Title and Source Number IEEE - PCI Mezzanine Card Specification (PMC) P1386.1 Draft 2.0 Institute of Electrical and Electronics Engineers, Inc. Publication and Sales Department 345 East 47th Street New York, New York 10017-21633 Telephone: 1-800-678-4333 Peripheral Component Interconnect (PCI) Local Bus Specification, PCI Local Bus...
  • Page 125 Publication Document Title and Source Number PowerPC Microprocessor Common Hardware Reference Platform A System Architecture (CHRP), Version 1.0 Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 E-mail: ldcformotorola@hibbertco.com AFDA, Apple Computer, Inc. P. O. Box 319...
  • Page 126 Related Specifications Computer Group Literature Center Web Site...

  • Page 127: Appendix B Specifications

    Specifications Specifications The following table lists the general specifications for the MVME240x VME processor module. The subsequent sections detail cooling requirements and EMC regulatory compliance. A complete functional description of the MVME240x boards appears in Chapter 3. Specifications for the optional PMCs can be found in the documentation for those modules.
  • Page 128 Specifications Table B-1. MVME240 x Specifications (Continued) Characteristics Specifications Relative humidity 10% to 80% Vibration (operating) 2 Gs RMS, 20Hz-2000Hz random Altitude (operating) 5000 meters (16,405 feet) Physical dimensions Height Double-high VME board, 9.2 in. (233 mm) (base board only) Front panel width 0.8 in.

  • Page 129: Cooling Requirements

    (base board and modules) at a velocity typically achievable by using a 100 CFM axial fan. Temperature qualification is performed in a standard Motorola VMEsystem chassis. Twenty-five-watt load boards are inserted in two card slots, one on each side, adjacent to the board under test, to simulate a high power density system configuration.

  • Page 130: Emc Regulatory Compliance

    EMC Regulatory Compliance module in environments having lower maximum ambients. Under more favorable thermal conditions, it may be possible to operate the module reliably at higher than 55° C with increased airflow. It is important to note that there are several factors, in addition to the rated CFM of the air mover, which determine the actual volume and speed of air flowing over a module.

  • Page 131: Introduction

    Slot 2 64-bit PCI extension and J23, J24 C-10 P2 I/O Pin Assignments The following tables furnish pin assignments only. For detailed descriptions of the various interconnect signals, consult the support information documentation for the MVME240x (contact your Motorola sales office).

  • Page 132: Pin Assignments

    Pin Assignments VMEbus Connector - P1 Two 160-pin DIN type connectors, P1 and P2, supply the interface between the base board and the VMEbus. P1 provides power and VME signals for 24-bit addressing and 16-bit data. Its pin assignments are set by the IEEE P1014-1987 VMEbus Specification and the VME64 Extension Standard.
  • Page 133 Connector Pin Assignments Table C-1. P1 VMEbus Connector Pin Assignments (Continued) ∗ VIRQ5 VA12 Not Used ∗ Not Used VIRQ4 VA11 Not Used ∗ VIRQ3 VA10 Not Used ∗ Not Used VIRQ2 Not Used ∗ VIRQ1 Not Used Not Used –12V +5VSTDBY +12V...

  • Page 134: Vmebus Connector - P2

    Pin Assignments VMEbus Connector - P2 Row B of the P2 connector provides power to the MVME240x, the upper eight VMEbus lines, and additional 16 VMEbus data lines as specified by the VMEbus specification Rows A, C, Z, and D of the P2 connector provide power and interface signals to a transition module, when one is used.
  • Page 135 Connector Pin Assignments Table C-2. P2 Connector Pin Assignment (Continued) PMC2_35 (J24-35) PMC1_46 (J14-46) VD24 PMC1_45 (J14-45) PMC2_34 (J24-34) PMC1_48 (J14-48) VD25 PMC1_47 (J14-47) PMC2_36 (J24-36) PMC2_38 (J24-38) PMC1_50 (J14-50) VD26 PMC1_49 (J14-49) PMC2_37 (J24-37) PMC1_52 (J14-52) VD27 PMC1_51 (J14-51) PMC2_39 (J24-39) PMC2_41 (J24-41) PMC1_54 (J14-54)

  • Page 136: Serial Port Connector - Debug (J2

    Pin Assignments Serial Port Connector - DEBUG (J2) A standard RJ45 connector located on the front plate of the MVME240x provides the interface to the asynchronous serial debug port. The pin assignments for this connector are as follows: Table C-3. DEBUG (J2)Connector Pin Assignments Ethernet Connector - 10BASET (J3) The 10BaseT/100BaseTx connector is an RJ45 connector located on the front plate of the MVME240x.

  • Page 137: Cpu Debug Connector - J1

    Connector Pin Assignments CPU Debug Connector - J1 One 190-pin Mictor connector with center row of power and ground pins is used to provide access to the Processor Bus and some miscellaneous signals. The pin assignments for this connector are as follows: Table C-5.
  • Page 138 Pin Assignments Table C-5. Debug Connector Pin Assignments (Continued) PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PA20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 PD32 PD33 PD34 PD35 PD36 PD37 Computer Group Literature Center Web Site...
  • Page 139 Connector Pin Assignments Table C-5. Debug Connector Pin Assignments (Continued) PD38 PD39 PD40 PD41 PD42 PD43 PD44 PD45 PD46 PD47 PD48 PD49 PA50 PD51 PD52 PD53 PD54 PD55 PD56 PD57 PD58 PD59 PD60 PD61 PD62 PD63 PDPAR0 PDPAR1 PDPAR2 PDPAR3 PDPAR4 PDPAR5 PDPAR6...
  • Page 140 Pin Assignments Table C-5. Debug Connector Pin Assignments (Continued) TSIZ0 TSIZ1 TSIZ2 CSE0 GLOBAL# CSE1 SHARED# DBWO# AACK# +3.3V ARTY# XATS# DRTY# TBST# TEA# DBG# DBB# ABB# TCLK_OUT CPUGNT0# CPUREQ0# C-10 Computer Group Literature Center Web Site...
  • Page 141 Connector Pin Assignments Table C-5. Debug Connector Pin Assignments (Continued) CPUREQ1# INT0# CPUGNT1# MCPI# INT1# SMI# MCPI1# CKSTPI# L2BR# CKSTPO# L2BG# HALTED L2CLAIM# TLBISYNC# TBEN SUSPEND# DRVMOD0 DRVMOD1 NAPRUN SRESET1# QREQ# SRESET0# QACK# HRESET# CPUCLK CPUCLK CPUCLK TRST# http://www.mcg.mot.com/literature C-11...

  • Page 142: Pci Expansion Connector - J6

    Pin Assignments PCI Expansion Connector - J6 One 114-pin Mictor connector with center row of power and ground pins is used to provide PCI/PMC expansion capability. The pin assignments for this connector are as follows: Table C-6. J6 - PCI Expansion Connector Pin Assignments +3.3V +3.3V PCICLK...
  • Page 143 Connector Pin Assignments Table C-6. J6 - PCI Expansion Connector Pin Assignments (Continued) PCIRST# C/BE1# C/BE0# C/BE3# C/BE2# AD11 AD10 AD13 AD12 AD15 AD14 AD17 AD16 AD19 AD18 AD21 AD20 AD23 AD22 AD25 AD24 AD27 AD26 AD29 AD28 AD31 AD30 http://www.mcg.mot.com/literature C-13...
  • Page 144 Pin Assignments Table C-6. J6 - PCI Expansion Connector Pin Assignments (Continued) PAR64 Reserved C/BE5# C/BE4# C/BE7# C/BE6# AD33 AD32 AD35 AD34 AD37 AD36 AD39 AD38 AD41 AD40 AD43 AD42 AD45 AD44 AD47 AD46 AD49 AD48 AD51 AD50 AD53 AD52 AD55 AD54 AD57...

  • Page 145: Pci Mezzanine Card Connectors - J11 Through J14

    Connector Pin Assignments PCI Mezzanine Card Connectors - J11 through J14 Four 64-pin SMT connectors, J11 through J14, supply 32/64-bit PCI interfaces and P2 I/O between the MVME240x board and an optional add- on PCI Mezzanine Card (PMC) in PMC Slot 1. The pin assignments for PMC Slot 1 are listed in the following two tables.

  • Page 146: Table C-8. J13 - J14 Pmc1 Connector Pin Assignments

    Pin Assignments Table C-7. J11 - J12 PMC1 Connector Pin Assignments (Continued) 47 AD12 AD11 AD10 AD09 AD08 +3.3V C/BE0# AD07 Not Used AD06 AD05 +3.3V Not Used AD04 Not Used +5V (Vio) AD03 Not Used Not Used AD02 AD01 Not Used AD00 ACK64#...
  • Page 147 Connector Pin Assignments Table C-8. J13 - J14 PMC1 Connector Pin Assignments (Continued) 33 GND AD48 PMC1_33 (P2-C17) PMC1_34 (P2-A17) 35 AD47 AD46 PMC1_35 (P2-C18) PMC1_36 (P2-A18) 37 AD45 PMC1_37 (P2-C19) PMC1_38 (P2-A19) 39 +5V (Vio) AD44 PMC1_39 (P2-C20) PMC1_40 (P2-A20) 41 AD43 AD42 PMC1_41 (P2-C21)

  • Page 148: Pci Mezzanine Card Connectors - J21 Through J24

    Pin Assignments PCI Mezzanine Card Connectors - J21 through J24 Four 64-pin SMT connectors, J21 through J24, supply 32/64-bit PCI interfaces and P2 I/O between the MVME240x board and an optional add- on PCI Mezzanine Card (PMC) in PMC Slot 2. The pin assignments for PMC Slot 2 are listed in the following two tables.

  • Page 149: Table C-10. J23 And J24 Pmc2 Connector Pin Assignments

    Connector Pin Assignments Table C-9. J21 and J22 PMC2 Connector Pin Assignments (Continued) 47 AD12 47 GND AD11 AD10 49 AD09 +5V (Vio) 49 AD08 +3.3V 51 GND 51 AD07 C/BE0# Not Used 53 AD06 53 +3.3V AD05 Not Used 55 AD04 55 Not Used 57 +5V...
  • Page 150 Pin Assignments Table C-10. J23 and J24 PMC2 Connector Pin Assignments (Continued) 31 AD49 31 PMC2_31 (P2-D21) PMC2_32 (P2-Z21) 33 GND AD48 33 PMC2_33 (P2-D22 PMC2_34 (P2-D23) 35 AD47 35 PMC2_35 (P2-Z23) AD46 PMC2_36 (P2-D24) 37 AD45 37 PMC2_37 (P2-D25) PMC2_38 (P2-Z25 39 +5V (Vio) AD44...

  • Page 151: Solving Startup Problems

    DTroubleshooting the MVME240x Solving Startup Problems In the event of difficulty with your MVME240x VME Processor Module, try the simple troubleshooting steps on the following pages before calling for help or sending the board back for repair. Some of the procedures will return the board to the factory debugger environment.
  • Page 152 Solving Startup Problems Table D-1. Troubleshooting MVME240x Modules (Continued) Condition Possible Problem Try This: II. There is a display A. The keyboard or Recheck the keyboard and/or mouse connections and power. on the terminal, mouse may be but input from the connected keyboard and/or incorrectly.
  • Page 153 Troubleshooting the MVME240x Table D-1. Troubleshooting MVME240x Modules (Continued) Condition Possible Problem Try This: IV. Continued 2. At the command line prompt, type in: env;d <CR> This sets up the default parameters for the debugger environment. 3. When prompted to Update Non-Volatile RAM, type in: y <CR>...
  • Page 154 Solving Startup Problems Table D-1. Troubleshooting MVME240x Modules (Continued) Condition Possible Problem Try This: VI. The board has A. There may be 1. Document the problem and return the board for service. failed one or more some fault in the 2.

  • Page 155: Glossary

    Glossary Abbreviations, Acronyms, and Terms to Know This glossary defines some of the abbreviations, acronyms, and key terms used in this document. An Ethernet implementation in which the physical medium is a 10Base-5 doubly shielded, 50-ohm coaxial cable capable of carrying data at 10 Mbps for a length of 500 meters (also referred to as thicknet).
  • Page 156 Glossary Attachment Unit Interface Battery Backed-up Random Access Memory BBRAM Having big-endian and little-endian byte ordering capability. bi-endian big-endian A byte-ordering method in memory where the address n of a word corresponds to the most significant byte. In an addressed memory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the most significant byte.
  • Page 157 The Green signals (G-Y) can be extracted by these two signals. Common Hardware Reference Platform (CHRP) A specification published by Apple, IBM, and Motorola which defines the devices, interfaces, and data formats that make up a CHRP-compliant system using a PowerPC processor.
  • Page 158 Ethernet A local area network standard that uses radio frequency signals carried by coaxial cables. The DRAM controller chip developed by Motorola for the Falcon MVME2600 and MVME3600 series of boards. It is intended to be used in sets of two to provide the necessary interface between the Power PC60x bus and the 144-bit ECC DRAM (system memory array) and/or ROM/Flash.
  • Page 159 FDDI Fiber Distributed Data Interface. A network based on the use of optical-fiber cable to transmit data in non-return-to-zero, invert-on- 1s (NRZI) format at speeds up to 100 Mbps. First-In, First-Out. A memory that can temporarily hold data so that FIFO the sending device can send data faster than the receiving device can accept it.
  • Page 160 (left to right) 3, 2, 1, 0, with 3 being the most significant byte. MBLT Multiplexed BLock Transfer Micro Channel Architecture MCA (bus) Motorola Computer Group Modified Frequency Modulation Musical Instrument Digital Interface. The standard format for MIDI recording, storing, and playing digital music. Multimedia Personal Computer...
  • Page 161 MPC105 The PowerPC-to-PCI bus bridge chip developed by Motorola for the Ultra 603/Ultra 604 system board. It provides the necessary interface between the MPC603/MPC604 processor and the Boot ROM (secondary cache), the DRAM (system memory array), and the PCI bus.
  • Page 162 Glossary Operating System. The software that manages the computer resources, accesses files, and dispatches programs. One-Time Programmable palette The range of colors available on the screen, not necessarily simultaneously. For VGA, this is either 16 or 256 simultaneous colors out of 262,144. parallel port A connector that can exchange data with an I/O device eight bits at a time.
  • Page 163 Instructions can be sent simultaneously to three types of independent execution units (branch units, fixed-point units, and floating-point units), where they can execute concurrently, but finish out of order. PowerPC is used by Motorola, Inc. under license from IBM. The first implementation of the PowerPC family of PowerPC 601™...
  • Page 164 All data in RAM is lost when the computer is turned off. Row Address Strobe. A clock signal used in dynamic RAMs to control the input of the row addresses. The PowerPC-to-PCI local bus bridge chip developed by Motorola Raven for the MVME2600 and MVME3600 series of boards. It provides the necessary interface between the PowerPC 60x bus and the PCI bus, and acts as interrupt controller.
  • Page 165 See 10base-5. thick Ethernet thin Ethernet See 10base-2. See 10Base-T. twisted-pair Ethernet Universal Asynchronous Receiver/Transmitter UART Universe ASIC developed by Tundra in consultation with Motorola, that provides the complete interface between the PCI bus and the 64-bit VMEbus. http://www.mcg.mot.com/literature GL-11...
  • Page 166 When data is copied from disk to main memory, the physical address is changed to the virtual address. VL bus See VESA Local bus (VL bus). MCG second generation VMEbus interface ASIC (Motorola) VMEchip2 MCG ASIC that interfaces between the PCI bus and the VMEchip2 VME2PCI device.
  • Page 167 EXtended Graphics Array. An improved IBM VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels. Luminance. This determines the brightness of each spot (pixel) on a Y Signal CRT screen either color or B/W systems, but not the color. http://www.mcg.mot.com/literature GL-13...
  • Page 168 Glossary GL-14 Computer Group Literature Center Web Site...

  • Page 169: Index

    Index Numerics bits per character 1-12, block diagram 10/100 BASET port MVME240x 16/32-bit timers 3-29 board information block board layout, MVME240x abbreviations, acronyms, and terms to know board placement 1-22 GL-1 board structure abort (interrupt) signal bridge ABT switch (S1) as Hawk function altitude (operating) ambient air temperature...
  • Page 170 Index console terminal processor/memory domain 4-10 preparing 1-12 VMEbus domain 4-11 cooling requirements counters 3-28 Auto Boot Abort Delay Auto Boot Controller Auto Boot Default String CPU LED (DS2) 2-3, Auto Boot Device Auto Boot Partition Number L2 Cache Parity Enable 6-12 debug console terminal Memory Size...
  • Page 171 forced air cooling MVME240x hardware 1-13 front panel PCI mezzanine cards 1-13 controls PMCs 1-13 MVME240x PMCspan 1-16, 1-18 front panels, using primary PMCspan 1-16 secondary PMCspan 1-18 interconnect signals general description interface MVME240x Ethernet 3-22 general-purpose software-readable header PCI bus 3-23 (S3) 1-8, 1-11...
  • Page 172 (Auto Boot Device) Memory Size Enable 6-11 parameter (Auto Boot Partition Number) memory sizes SDRAM 3-14 parameter (L2 Cache Parity Enable) Motorola Computer Group documents 6-12 MPC750 processor parameter (Memory Size) 6-11 MPIC (MultiProcessor Interrupt Controler) parameter (Negate VMEbus SYSFAIL* 3-28...
  • Page 173 PCI expansion slot arbiter PMC2 connector pin assignments, J21 and PCI Host Bridge (PHB) 3-27 C-18 PCI Mezzanine Card (PMC) PMC2 connector pin assignments, J23 and PCI mezzanine cards C-19 slots PMC2 LED (DS3) PCI Mezzanine Cards (PMCs) PMCs PCI-ISA Bridge (PIB) controller 3-26 installing 1-13...
  • Page 174 Index programming the MVME240x serial port, MVME240x prompt, debugger 5-11 set environment to bug/operating system prompts (ENV) PPCBug setup terminal 1-22 SGS-Thomson MK48T559 timekeeper de- vice Raven MPU/PCI bus bridge controller ASIC shielded cables 3-6, size of base board readable jumpers 1-11 SNAPHAT battery real-time clock...
  • Page 175 timers, programmable 3-28 timers, via Universe chip troubleshooting procedures troubleshooting the MVME240x 5-10 Typical Single-width PMC Module Place- ment on MVME240x 1-15 Universe ASIC 3-25 Universe VMEbus interface ASIC 2-3, 4-3, 4-4, 4-9, 4-11 unpacking the hardware uppercase 5-12 using the front panels vibration (operating) VME Processor Module board layout...
  • Page 176 Index IN-8 Computer Group Literature Center Web Site...
  • Page 177 MVME2400-Series Cover Single Board Computer Installation and Use 34 pages ® ™ 1/8” spine 36 - 84 pages ® ™ 3/16” & 1/4” spine 86 - 100 pages ® ™ 5/16” spine MVME2400-Series Single Board Computer Installation and 102 - 180 pages 3/8”...

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