System Clock And Cpu Clock Switching Procedure - NEC 78014Y Series User Manual

7.6.2 System clock and CPU clock switching procedure

This section describes switching procedure between system clock and CPU clock.
System Clock
CPU Clock
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(1)The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released
by setting the RESET signal to high level, the main system clock starts oscillation. At this time, the oscillation
stabilization time (2
After that, the CPU starts executing the instruction at the minimum speed of the main system clock (6.4 µ s when
operated at 10.0 MHz).
(2)After the lapse of a sufficient time for the V
processor clock control register (PCC) is rewritten and maximum-speed operation is carried out.
(3)Upon detection of a decrease of the V
switched to the subsystem clock (which must be in an oscillation stabilization state).
(4)Upon detection of V
of the main system clock is started. After the lapse of time required for stabilization of oscillation, the PCC is
rewritten and maximum-speed operation is resumed.
Caution
Figure 7-8. System Clock and CPU Clock Switching
V
DD
RESET
Interrupt
Request
Signal
Internal Reset Operation
18
/f ) is secured automatically.
X
voltage reset due to an interrupt request signal, 0 is set to PCC bit 7 (MCC) and oscillation
DD
When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization time has been secured by the program before switching back to
the main system clock.
CHAPTER 7 CLOCK GENERATOR
f f
X X
Minimum Maximum Speed
Speed Operation
Operation
Wait (26.2 ms : @ 10.0 MHz)
voltage to increase to enable operation at maximum speed, the
DD
voltage due to an interrupt request signal, the main system clock is
DD
f f
XT
Subsystem Clock High-Speed
Operation Operation
X
169