CHAPTER 3 THEORY OF OPERATION
HL-1270N
Fig. 3-6 shows the block diagram of the main PCB of the HL-1270N printer.
A S I C
CPU Core
(MB86832)
Oscillator (32.7MHz)
Reset Circuit
BUS
INT
Address Decoder
DRAM Control
Program + Font ROM
4.0 Mbytes
Timer
Flash ROM
(2.0 Mbytes)
FIFO
RAM
CDCC Parallel I/O
To PC
(4.0 Mbytes)
To PC
USB I/O
Option RAM (SIMM)
(max. 32Mbytes)
Soft Support
EEPROM (4096 x 8 bits)
EEPROM I/O
Engine Control I/O
To Engine PCB
To PC
Network Board
PCI Bus Control
or Hub
Fig. 3-6
3-6