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OVR — Overrun
This bit is set by the ISPI controller when a new value is loaded into the RX data reg-
ister due to an overrun event. An overrun occurs whenever the RX data register is
updated while holding previously received data that has not been read. This could
occur when pin SPI_EN becomes inactive and the bit timer has already timed out, or
when the bit counter times out a second time while SPI_EN remains continuously
asserted. It could also be set in interval or manual master mode if the RX data regis-
ter is not read between transfers. In these cases, the OVR bit may be ignored if
appropriate.
0 = No overrun event has occurred
1 = An overrun event has occurred
This bit is cleared by writing it to zero or by reset.
IRQ — Interrupt Request
This register bit is cleared on either a write or a read of the ISPI data register, and
when set indicates that an interrupt has been requested.
0 = No interrupt has been requested
1 = An interrupt has been requested
XCH — Exchange
This bit indicates whether the state machine is performing a transfer. In manual
mode, XCH is set by writing the ISPI data register. In interval mode, XCH is set auto-
matically by the interval timer. In slave mode, XCH is set when pin SPI_EN is
asserted and is negated briefly once the counters determine the completion of a
transfer. It is then reasserted if SPI_EN is still asserted. In all modes, XCH is reset
upon completion of a transfer.
0 = SPI is idle or interval timer is operating
1 = Initiate exchange or exchange in progress
12.5 ISPI Programming Examples
12.5.1 Manual Mode Example
Manual mode is the simplest of the transfer methods.
Assume that the transfer to be performed is bidirectional, and the receive data is 12
bits. The data to be sent is 0x0013, and the external device will receive and keep all
12 bits. The external device is such that PHA=1, POL=0 is desired, with an active low
enable. An interrupt is required following the transfer to indicate when data is avail-
able. The device accepts data at a clock rate between 100 kHz and 1 MHz, and the
MMC2001 uses a 16.38-MHz clock.
To program the ISPI to perform such a transfer:
1. Write ISPI register SPCR to 0x4E4B.
2. Write ISPI register SPDR to 0x0013.
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
INTERVAL MODE SERIAL PERIPHERAL INTERFACE
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
12-9
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