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Synchronous sampling frequency:
Bits per frame :
Data :
Synchronisation :
Synchronisation status :
State of CT105 / CT109:
Speed :
NIC :
600/1200 bps synchronisation adaption:
State of CT108 / CT107:
Flow control (CT106):
Table 2-1 Rate Adaptation Methods.
First the two data ports try to synchronise using a synchronisation pattern in the frame
structure. If this pattern is detected without errors, then synchronisation is established.
Synchronisation must be achieved in both directions. Once synchronisation is established
the user-data and the interface control signals can be transferred between the two parties
and the 64 kbps transparent channel is available to the DTEs.
Each DCE receives the relevant interface signals (control signals and the user data) from
the DTE and inserts them into the correct frame position in the 64 kbps user channel. This
user channel is multiplexed by the DCE into the 152 kbps 2B+D line to the DLC. The
DLC-line interface demultiplexes the 64 kbps user channel from the 2B+D line and inserts
it in a timeslot in the 2 Mbps highway to the PSC/PMC. The 64 kbps signal is transferred
to the opposite DLC, via the PSC/PMC and the switching network (and, if necessary, inter-
unit links). The receiving DLC extracts the 64 kbps user channel from the 2 Mbps highway
and multiplexes it into the user channel of the 2B+D line to the destination DCE. The data
and control signals are extracted from the 2B+D line by the DCE and passed to the DTE.
A transparent digital path has thus been established between the two DTEs.
Data rate adaption is performed by a dedicated chip in ERGOLINE, SOPHO-SET,
SOPHO-LAM or LAM; for SOPHO-SET, SOPHO-LAM or LAM the OQ 1505 or the OQ
1509. A summary of the most important features of these chips is given below.
PROPRIETARY
96kHz
32
24
4
1
3
-
-
-
-
-
X.30
V.110
-
-
80
80
48
48
17
17
-
-
2
2
3
3
3
3
1
1
4
4
2
2
17
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