Hardware Interrupt - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
3.4

Hardware Interrupt

Hardware interrupt suspends the active program execution by the CPU in response to
an interrupt request signal generated by a peripheral function, resulting in transfer of
control to the user-defined interrupt handling program. Extended intelligent I/O service
2
OS), μDMAC, external interrupts, and other similar processes are also executed as a
(EI
type of hardware interrupt.
■ Function of Hardware Interrupt
●
Function of hardware interrupt
Hardware interrupt makes comparison between the interrupt level of the interrupt request signal which a
peripheral function outputs and the interrupt level mask register (ILM) in the CPU's processor status (PS).
This interrupt also refers the contents of the I flag in PS, by hardware, to determine whether the interrupt is
acceptable.
Once the hardware interrupt is accepted, the contents of the registers and their related data in the CPU are
automatically saved in the system stack. The level of the currently requested interrupt is stored in the ILM.
Then, control branches to the associated interrupt vector.
●
Multiple interrupts
Multiple hardware interrupts can be activated.
●
2
EI OS
At the completion of transfer, a hardware interrupt is activated although EI
function between EI
2 OS process is in progress, all the other interrupt requests and μDMAC requests remain pending.
an EI
●
μDMAC
At the completion of transfer, a hardware interrupt is activated although μDMAC is an automatic transfer
function between memory and I/O. Further, μDMAC cannot be activated in a multiple manner. While an
μDMAC process is in progress, all the other interrupt requests and EI
●
External interrupt
The external interrupt (including a wake-up interrupt) is accepted as a hardware interrupt through the
peripheral function (its interrupt request detector circuit).
●
Interrupt vector
The interrupt vector table, referred during execution of the interrupt process, is assigned to the FFFC00
FFFFFF
vectors, see Section "3.2 Interrupt Cause and Interrupt Vector"
CM44-10137-6E
2
OS/memory and I/O. Further, EI
memory for shared with software interrupt. For allocations of interrupt numbers and interrupt
H
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 3 INTERRUPT
2
OS is an automatic transfer
2
OS cannot be activated in a multiple manner. While
2
OS requests remain pending.
3.4 Hardware Interrupt
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