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PREFACE Thank you for selecting FUJITSU Semiconductor Devices. The FUJITSU MB90580 series has been developed as one general-application version of the ® *16LX series of original 16-bit one-chip microcontrollers for ASIC (application specific IC) applications. This manual describes the functions and operations of the MB90580 series, and is intended for use by engineers actually designing products using these semiconductors.
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Chapter 12 COMMUNICATION PRESCALER This section describes the MB90580 series communication prescaler. Chapter 13 UART This section describes the function and operation of the MB90580 UART. Chapter 14 IE BUS This section describes the functions and operation of the MB90580 series IE Bus. Chapter 15 8/16-BIT PPG This section describes the functions and operation of the MB90580 series 8/16-bit PPG.
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6.4.3 Watch mode ........................69 6.4.4 Stop mode ...........................69 6.4.5 Hardware standby mode .....................70 6.4.6 CPU intermittent operation function ..................70 6.4.7 Setting the main clock oscillation stabilization waiting period ..........71 6.4.8 Switching the machine clock ....................71 6.4.9 State transition ........................73 Chapter 7 Interrupt ............................81 7.1 Outline ............................81 7.2 Causes of Interrupt ........................82 7.3 Interrupt Vector ..........................83...
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9.4 Operations ...........................112 9.4.1 External interrupts ......................112 9.4.2 DTP operation ........................113 9.4.3 Switching between external interrupt and DTP requests ...........114 9.5 Notes on use ..........................115 9.5.1 Conditions on the externally connected peripheral when DTP is used ......115 9.5.2 Recovery from standby ......................115 9.5.3 External interrupt/DTP operation procedure ..............115 9.5.4 External interrupt request level ..................115 Chapter 10 Delayed Interrupt Generation Module ..................117...
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13.3.6 Telegraph length set register (DEWR) ................152 13.3.7 Status register upper byte (STRH) ..................153 13.3.8 Status register lower byte (STRL) ...................155 13.3.9 Lock read register (LRRH, LRRL) ...................157 13.3.10 Master address read register (MARH, MARL) ...............158 13.3.11 Multiaddress, control bit read register (DCRR) ..............159 13.3.12 Telegraph length read register (DERR) .................160 13.3.13 Read data buffer (RDB) ....................161 13.3.14 Write data buffer (WDB) ....................162...
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16.3 Registers and Register Details ....................221 16.3.1 Control status registers (ADCS1 and ADCS2) ..............222 16.3.2 ADCR1 and ADCR0 (Data registers) ................226 16.4 Operations ..........................228 16.5 Notes on use ..........................234 16.5.1 Other considerations ......................234 Chapter 17 D/A Converter ..........................235 17.1 Outline ............................235 17.2 Block Diagram ...........................236 17.3 Registers and Register Details ....................237 17.3.1 DAT0/1 ( D/A data register) .....................238...
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21.2 Block Diagram ...........................291 21.3 Registers and Register Details ....................292 21.3.1 Program Address Detect Register 0/1 (PADR0/PADR1) ..........292 21.3.2 Program Address detect Control Status Register (PACSR) ..........293 21.4 Operations ..........................294 21.5 Application Example ........................295 Chapter 22 ROM Mirroring Module .......................299 22.1 Outline ............................299 22.2 Block Diagram ...........................299 22.3 Registers and Register Details ....................300...
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FIGURES Chapter 1 Overview ............................1 Figure 1.3a Block Diagram of MB90580 Series ..................4 Figure 1.4a Pin Assignment of MB90580 (LQFP-100)................5 Figure 1.4b Pin Assignment of MB90580 (QFP-100)................6 Figure 1.6a Using external clock ......................14 Figure 1.6b Connection of Power pins ....................14 Chapter 2 CPU ..............................15 Figure 2.1.1a Sample relationship between F2MC-16LX system and memory map ......
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Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions ..........51 Figure 5.2a Watchdog Timer, Timebase Timer, and Watch Timer Block Diagram ......52 Figure 5.4.1a Watch-dog timer operation.................... 59 Chapter 6 Low Power Control Circuit ......................61 Figure 6.2a Low-power consumption control circuit and clock generator ........... 62 Figure 6.4.8a Clock Selection State Transition Diagram (1) ...............
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Chapter 12 UART ............................123 Figure 12.2a Block diagram of UART....................124 Figure 12.3a Registers of UART ....................... 125 Figure 12.4.3a Transfer data format (modes 0 and 1) ..............134 Figure 12.4.4a Transfer data format (mode 2) .................. 135 Figure 12.4.5a Timing to set PE, ORE, FRE, and RDRF (mode 0) ..........137 Figure 12.4.5b Timing to set ORE, FRE, and RDRF (mode 1) ............
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Figure 15.4.7a Counter State Transitions ..................218 Chapter 16 A/D Converter ..........................219 Figure 16.2a Block Diagram of A/D converter................... 220 Figure 16.3a Registers of A/D Converter ..................221 Figure 16.3.1a Control Status Registers ................... 222 Figure 16.3.2a Data Registers ......................226 Figure 16.4a Flow chart of A/D Conversion ..................
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Figure 22.2a Block Diagram of ROM Mirroring Module ..............299 Figure 22.3a Register of ROM Mirroring Module ................300 Figure 22.3b Memory in Single Chip Mode ..................301 Figure 22.3c Memory in Internal ROM External Bus Mode............... 301 Appendix A I/O Map ............................303 Appendix B Instructions ..........................309 Fig.
Chapter 1: Overview The MB90580 series 16-bit microcontrollers are designed for applications that require high-speed real-time processing. These microcontrollers feature functions that are suitable for controlling car audio and electronic appliances. 1.1 Features • Clock Embedded PLL Clock Multiplication Circuit Operating clock (PLL clock) can e selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz).
1.2 Product Lineup 1.2 Product Lineup Internal Configuration Table 1.2a lists the product lineup of the MB90580 series. All products are functionally identical except for ROM and RAM sizes. Table 1.2a MB90580 series product lineup MB90V580 MB90583 MB90F583 ROM size ______ Mask ROM Flash ROM...
1.5 Pin Functions Table 1.5b Pin functions (2/4) LQFP Pin name I/O Circuit Function General-purpose I/O port SOT0 pin when the SOE bit of the UMC register is ’1’ Open drain output port when OD41 of the open drain control setting regis- ter (ODR4) is set to ’1’...
1.5 Pin Functions Table 1.5c Pin functions (3/4) LQFP Pin name I/O Circuit Function General-purpose I/O port Analog input pin (AN6) during A/D converter operation (CMOS/H) SCK4 UART4 serial data output (SOT4) pin General-purpose I/O port (CMOS/H) Analog input pins (AN7) during A/D converter operation 0.1uf capacitor connection pin for voltage supply stabilization.
1.5 Pin Functions Table 1.5d Pin functions (4/4) LQFP Pin name I/O Circuit Function General-purpose I/O port A pull-up resistor can be assigned (RD63=’1’) by using the pull-up resistor setting register (RDR6). (D63=’1’: Invalid when set as output) (CMOS/H) PPG00 PPG00 output when PPG is enabled General-purpose I/O port A pull-up resistor can be assigned (RD64=’1’) by using the pull-up resistor...
1.5 Pin Functions Table 1.5f I/O circuit format (2) Class Circuit Remarks • CMOS level output • With open drain control • Hysteresis input with standby contro Open drain control signal Standby control signal • CMOS level output • Hysteresis input with standby control Standby control signal •...
1.5 Pin Functions Table 1.5g I/O circuit format (3) Class Circuit Remarks • CMOS level output • Hysteresis input with standby control • Analog output • Shared with DA output DA Output Standby control signal • CMOS level output • Hysteresis input MB90580 series Chapter 1: Overview...
1.6 Handling the Device 1.6 Handling the Device (1) Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions: A voltage higher than Vcc or lower than Vss is applied to an input or output pin. A voltage higher than the rated voltage is applied between Vcc and Vss. The AVcc power supply is applied before the Vcc voltage.
Chapter 2: 2.1 CPU The F MC-16LX CPU core is a 16-bit CPU designed for applications that require high-speed real-time processing, such as home-use or vehicle-mounted electronic appliances. The F MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing. In addition to 16-bit data, the F MC-16LX CPU core can process 32-bit data by using an internal 32-bit accumulator.
2.1 CPU 2.1.1 Memory space Outline of CPU memory space An F MC-16LX CPU has a 16-Mbyte memory space. All data program input and output managed by the MC-16LX CPU are located in this 16-Mbyte memory space. The CPU accesses the resources by indicating their addresses using a 24-bit address bus.
2.1 CPU Address generation types The F MC-16LX CPU has two address generation methods. One is the linear method in which an entire 24-bit address is specified by an instruction. The other method is the bank method in which the high-order eight bits of an address is specified by an appropriate bank register while the low-order 16 bits of the same address is specified by an instruction.
2.1 CPU The 64-Kbyte bank specified by the PCB is called a program (PC) space. The PC space contains instruction codes, vector tables, and immediate value data, for example. The 64-Kbyte bank specified by the DTB is called a data (DT) space. The DT space contains readable/ writable data, and control/data registers for internal and external resources.
2.1 CPU Multi-byte data allocation in memory space Figure 2.1.1d is a diagram of multi-byte data configuration in memory. The low-order eight bits of a data item are stored at address n, then address n+1, address n+2, address n+3, etc. 01010101 11001100 11111111...
2.1 CPU 2.1.2 Registers The F MC-16LX registers are largely classified into two types: special registers in the CPU and general-purpose registers in memory. The special registers are dedicated internal hardware of the CPU, and their applications are limited by the CPU architecture. The general-purpose registers share the CPU address space with RAM.
2.1 CPU General-purpose registers The F MC-16LX general-purpose registers are located from addresses 000180H to 00037FH (maximum configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses are currently being used as a register bank. Each bank has the following three types of registers. These registers are mutually dependent as described in Figure 2.1.2b.
2.1 CPU Accumulator (A) The A register consists of two 16-bit arithmetic operation registers (AH and AL). The A register is used as a temporary storage for operation results and transfer data. During 32-bit data processing, AH and AL are used together.
2.1 CPU User stack pointer (USP) and system stack pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data in the event of a push/pop instruction or subroutine execution. The USP and SSP registers are used by stack instructions.
2.1 CPU Processor status (PS) The PS register consists of the bits controlling the CPU Operation and the bits indicating the CPU status. As shown in Figure 2.1.2g, the high-order byte of the PS register consists of a register bank pointer (RP) and an interrupt level mask register (ILM).
2.1 CPU (2) Register bank pointer (RP) The RP register indicates the relationship between the general-purpose registers of the F2MC-16LX and the internal RAM addresses. Specifically, the RP register indicates the first memory address of the currently used register bank in the following conversion expression: [00180H + (RP)*10H] (see Figure 2.1.2i).
2.1 CPU Register bank A register bank consists of eight words. The register bank can be used as the following general-purpose registers for arithmetic operations: byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register bank can be used as instruction pointers. Table 2.1.2b lists the functions of the registers.
2.1 CPU Program counter bank register (PCB) <Initial value: Value in reset vector> Data bank register(DTB) <Initial value: 00H> User stack bank register(USB) <Initial value: 00H> System stack bank register(SSB) <Initial value: 00H> Additional data bank register(ADB) <Initial value: 00H> Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is allocated.
2.1 CPU 2.1.3 Prefix codes Placing a prefix code before an instruction partially changes the operation of the instruction. Three types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix. Bank select prefix The memory space used for accessing data is determined for each addressing mode.
2.1 CPU Common register bank prefix (CMR) To simplify data exchange between multiple tasks, the same register bank must be accessed relatively easily regardless of the RP value. When CMR is placed before an instruction that accesses a register bank, that instruction accesses the common bank (the register bank selected when RP=0) at addresses from 000180H to 00018FH regardless of the current RP value.
2.1 CPU Restrictions on interrupt disable instructions and prefix instructions When a prefix code is placed before an interrupt disable instruction, the prefix code affects the first instruction after the code other than the interrupt disable instruction. Interrupt disable instruction •...
Chapter 3: Memory 3.1 Memory Access Modes In the F MC-16LX, there are several modes for access methods, access areas, and test methods. In this module, the following classifications apply: Table 3.1a Memory Access Mode Access Mode Operation Mode Bus Mode (External data bus width) Single Chip ———...
3.1 Memory Access Modes 3.1.1 Mode pins Table 3.1.1a describes the operations specified by combinations of the MD2 to MD0 external pins. Table 3.1.1a Mode pins and modes External Mode pin setting Reset vector Mode name data bus Remarks MD2 MD1 MD0 access area width 0 0 0...
3.1 Memory Access Modes 3.1.2 Mode data Mode data is stored at FFFFDF of main memory and used for controlling the CPU operation. This data is fetched during a reset sequence and stored in the mode register inside the device. The mode register value can be changed only by a reset sequence.
3.1 Memory Access Modes 3.1.3 Bus Mode Figure 3.1.3a shows correspondence between the access areas and physical addresses for each bus mode. FFFFFF Address #1 FE0000 010000 (FF bank image) (FF bank image) Address #2 004000 002000 Address #3 : No access : Internal access 000100 0000C0...
3.1 Memory Access Modes Recommended setting Table 3.1.3a lists a sample recommended setting of mode pins and mode data. Table 3.1.3a Sample recommended setting of mode pins and mode data Sample setting × Single chip Internal ROM and external bus mode, 16-bit bus Internal ROM and external bus mode, 8-bit bus External ROM and external bus mode, 16-bit bus, vector 16 bus width External ROM and external bus mode, 8-bit bus...
3.2 External Memory Access 3.2 External Memory Access To access external memory and peripherals, the F MC-16LX supplies the following address, data, and control signals: (P37) Machine cycle clock (KBP) (P36) External ready input pin WRHX (P33) : Write signal for high-order 8 bits of data bus WRLX (P32) Write signal for low-order 8 bits of data bus...
3.2 External Memory Access 3.2.2 Registers and Register details Automatic ready function selection register Bit No. Address: 0000A5 — — IOR0 IOR1 HMR1 HMR0 LMR1 LMR0 ARSR Read/write Initial value External address output control register Bit No. Address: 0000A6 HACR Read/write Initial value Bus control signal selection register...
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3.2 External Memory Access 3.2.2.1 Automatic ready function selection register Bit No. Address: 0000A5 IOR0 ARSR IOR1 HMR1 HMR0 LMR1 LMR0 Read/write Initial value [bits 15 and 14]: IOR1 and IOR0 These bits specify the automatic wait function for external access to the area between 000000 0000FF IOR1 IOR0...
3.2 External Memory Access 3.2.2.2 External address output control register Bit No. Address: 0000A6 HACR Read/write Initial value This register controls the external output of addresses (A19 to A16). The bits corresponds to addresses A19 to A16, controlling the address output pins as described below. Table 3.2.0a Selecting the high-order address bit output control The corresponding pin is used as an address output (Axx).
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3.2 External Memory Access 3.2.2.3 Bus control signal selection register Bus control signal selection register Bit No. Address: 0000A7 — IOBS HMBS LMBS ECSR Read/write Initial value This register is used to set the bus control function in external bus mode. This register cannot be accessed when the device is in single chip mode.
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3.2 External Memory Access [bit 11]: HMBS This bit specifies the bus size when an area between 800000 and FFFFFF is externally accessed in 16-bit external data bus mode. The size is controlled as described below. 16-bit bus size access [default in mode other than external vector mode 2] 8-bit bus size access [default in external vector mode 2] This bit is initialized to ’1’...
3.2 External Memory Access 3.2.1 Operations MB90580 has a variety of access method and access area modes. See Section 3.1 ,“Memory Access Modes” (1) External memory access control signals External memory is accessed in three cycles while the ready function is not used. Figure 3.2.4 shows the concept of external access timing.
3.2 External Memory Access (2) Ready function When the RYE bit of the bus control signal selection register (EPCR) is set to ’1,’ a wait cycle is inserted while an L level signal appears at the R36/RDY pin in the event of an access to an external area. Thus, the access cycle can be extended.
3.2 External Memory Access When the RYE bit of EPCR is set to ’1,’ the wait cycle continues if an L level signal appears at the R36/RDY pin at the end of either automatic ready cycle. (3) Hold function When the HDE bit of EPCR is set to ’1,’ the external bus hold function by the P34/HRQ and P35/HAKX pins is enabled.
Chapter 4: Clock and Reset 4.1 Clock Generator The clock generator controls internal clock operation, including such functions as sleep, timer, stop, and PLL multiplication. This internal clock is called the machine clock, and one cycle of the machine clock is called a machine cycle.
4.2 Reset Causes 4.2 Reset Causes When a reset cause occurs, F MC-16LX terminates the currently executing processing and waits for the release of reset signal. A reset can be caused by the following factors: Power-on reset Hardware standby release Watch-dog timer overflow External reset request via RSTX pin Reset request by software...
When using the F MC-16LX in single chip mode or internal ROM external bus mode, Fujitsu recommends specifying internal vector mode. The bus mode after the reset vector and mode data are read is specified by the mode data.
Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions 5.1 Outline Watch-Dog Timer The watchdog timer consists of 2-bit counter that uses to carry signal from the 18-bit timebase timer or the 15-bit watch timer as a clock source, a control register, and a watchdog reset controller. The watch-dog timer function enables detection of program surge.
5.3 Registers and register details 5.3 Registers and register details Watch-Dog timer control register Bit number Address : 0000A8 ERST SRST PONR STBR WRST WDTC Read/write Initial value Timer base timer control register Bit number Address: 0000A9 Reserved TBTC TBIE TBOF TBC1 TBC0...
5.3 Registers and register details 5.3.1 WDTC (Watch-Dog Timer Control Register) Watch-Dog timer control register Bit number Address : 0000A8 ERST SRST PONR STBR WRST WDTC Read/write Initial value Don’t use read-modify-write command to access this register, otherwise malfunction will occur. [bits 7 to 3] PONR, STBR, WRST, ERST, and SRST These flags indicate the reset causes.
5.3 Registers and register details Table 5.3.1b Watchdog Timer Interval Selection Bits Interval Time (Source oscillation: 4 MHz) WDCS/ Minimum Maximum Approx. 3.58 ms Approx. 4.61 ms Approx. 14.33 ms Approx. 18.43 ms Approx. 57.23 ms Approx. 73.73 ms Approx. 458.75 ms Approx.
5.3 Registers and register details 5.3.2 TBTC (Time Base Timer Control Register) Timer base timer control register Bit number Address: 0000A9 Reserved TBIE TBOF TBC1 TBC0 TBTC Read/write (R/W) (R/W) (R/W) (R/W) Initial value Note: Don’t use read-modify-write command to access this register, otherwise malfunction will occur.
5.3 Registers and register details 5.3.3 Watch Timer Control Register (WTC) Watch timer control register Bit number Address: 0000AA WDCS WTIE WTOF WTC2 WTC1 WTC0 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value [Bit 7] WDCS This bit selects whether to use the clock signal from the watch timer or from the timebase timer for the watchdog timer input clock when the main clock and PLL clock are selected.
5.3 Registers and register details Table 5.3.3a Watch Timer Interval Selection Interval time when WTC2 WTC1 WTC0 subclock is 32 kHz 15.625 ms 31.25 ms 62.5 ms 0.125 s 0.250 s 0.500 s 1.000 s – Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions MB90580 Series...
5.4 Operation 5.4 Operation 5.4.1 Watch-Dog Timer The watch-dog timer function enables detection of program surge. If the watch-dog timer is not accessed within the specified time due to, for example, a program surge, the watch-dog timer resets the system. (1) Activation The watch-dog timer is activated by writing ’0’...
5.4.2 Time Base Timer The time base timer functions as a watch-dog timer clock source, timer for waiting for the oscillation to sta- bilize, and interval timer for generating interrupts at specified intervals. (1) Time base counter The time base counter consists of an 18-bit counter for a clock generated by dividing the source oscillation input by two.
Chapter 6: Low Power Control Circuit 6.1 Outline The following are the operating modes: PLL clock mode, PLL sleep mode, PLL watch mode, pseudo-watch mode, main clock mode, main sleep mode, main watch mode, main stop mode, subclock mode, sub sleep mode, sub watch mode, sub stop mode, and hardware standby mode. Aside from the PLL clock mode, all of the other operating modes are low power consumption modes.
6.3 Registers and register details [Bit 4] RST Writing a "0" to this bit generates an internal reset signal in three machine cycles. Writing a "1’ to this bit has no effect. When this bit is read, a "1" is returned. [Bit 3] TMD Writing a "0"...
6.3 Registers and register details 6.3.2 CKSCR (Clock selection register) Clock selection register Bit No. Address: 0000A1 CKSCR Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value [Bit 15] SCM This bit indicates whether the main clock or the subclock is selected as the machine clock. When this bit is "0", it indicates that the subclock is selected;...
6.3 Registers and register details [Bit 10] MCS This bit selects either the main clock or the PLL clock as the machine clock. When a "0" is written to this bit, the PLL clock is selected; when a "1" is written to this bit, the main clock is selected. If a "0" is written to this bit while it is "1", the oscillation stabilization waiting period for the PLL clock is generated;...
6.4 Operations 6.4 Operations The status of each chip block in each operating mode is shown in Table 6.4a Table 6.4a Low Power Consumption Mode Operating Statuses Transition Main Peripheral Exit Clock Pins condition oscillation oscillation method SCS=0 Reset Subclock Operating Stopped Operating...
6.4 Operations 6.4.1 Sleep mode Transition to sleep mode The standby control circuit is set to sleep mode by writing a "1" to the SLP bit, a "1’ to the TMD bit, and a "0" to the STP bit in the low power consumption mode control register. In sleep mode, only the clock sup- plied to the CPU is stopped;...
6.4 Operations processing resumes from the instruction that follows the last instruction that put the device into pseudo-watch mode. 6.4.3 Watch mode Transition to watch mode The standby control circuit is set to watch mode by writing a "0" to the TMD bit in the low power con- sumption mode control register.
6.4 Operations Exiting stop mode The standby control circuit releases stop mode when a reset signal is input or when an interrupt is generated. If stop mode was released by a reset source, the device enters the reset state after stop mode is released.
6.4 Operations In addition, the instruction execution time when the CPU intermittent operation function is used can be calculated by adding a compensation factor (the number of register, on-chip memory, on-chip resource, and external bus access multiplied by the number of pause cycles) to the normal execution time. Peripheral clock CPU clock Intermittent operation pause cycle...
6.4 Operations Machine clock initialization The MCS bit and the SCS bit are not initialized by a reset caused by an external pin or the RST bit. After other types of resets, these bits are each initialized to "1". Figure 6.4.8a and Figure 6.4.8b show the clock selection state diagram. Power on ⇒...
6.4 Operations MCS: MCS bit (clock selection register) (PLL clock mode is selected when MCS = 0) SCS: SCS bit (clock selection register) (sub-clock mode is selected when SCS = 0) STP: STP bit (low power consumption mode register) (sleep mode is selected when SLP = 0) SLP: SLP bit (low power consumption mode register) (sleep mode is selected when SLP = 0) TMD:...
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6.4 Operations Table 6.4.9a List of Transition Conditions (Continued) State before transition Transition conditions State after transition 02 Main oscillation stabilization waiting period completed Main mode Main oscillation stabiliza- 03 Reset initiated or interrupt tion 04 SCS = 0 written Sub mode SM transition mode 27 TMD = 1•STP = 0•SLP = 1 written...
6.4 Operations Table 6.4.9a List of Transition Conditions (Continued) State before transition Transition conditions State after transition 49 Main → sub-clock switching timing wait completed Sub-sleep MS transition sleep 50 Interrupt or reset initiated MS transition mode 54 PLL → main clock switching timing wait completed MS transition sleep PS transition sleep 55 Interrupt or reset initiated...
Chapter 7: Interrupt 7.1 Outline The F MC-16LX has interrupt functions that terminate the currently executing processing and transfer control to another specified program when a specified event occurs. There are four types of interrupt functions: Hardware interrupt: ........Interrupt processing due to an internal resource event Software interrupt: ........
7.4 Hardware Interrupt 7.4 Hardware Interrupt 7.4.1 Overview In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user. This function is called the hardware interrupt function.
7.4 Hardware Interrupt updates the ILM of PS to a level value of the received interrupt, sets the S flag, then performs branch processing. As a result, the interrupt processing program defined by the user is executed next. Figure 7.4.3a illustrates the flow from the occurrence of a hardware interrupt until there is no interrupt request in the interrupt processing program.
7.4 Hardware Interrupt The time required for the CPU to execute the interrupt processing in steps is shown below. Interrupt start 24 + 6 x Table 7.4.3a machine cycles Interrupt return 15 + 6 x Table 7.4.3a machine cycles (RETI instruction) Table 7.4.3a Compensation values for interrupt processing cycle count Address indicated by the stack pointer Cycle count compensation value...
7.4 Hardware Interrupt 7.4.4 Hardware Interrupt Ocurrence When Internal Resource Is Being Accessed When internal I/O area is being asscessed, the CPU will not response to hardware interrupt immediately, there will be one instruction delay. Please refer to Chapter 2, section 2.1.3 for details. 7.4.5 Interrupt Inhibit Instruction If F MC-16LX is executing interrupt inhibit instructions, the CPU will not response to hardware interrupt...
7.5 Software Interrupt 7.5 Software Interrupt 7.5.1 Overview In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program defined by the user. This is called the software interrupt function.
7.5 Software Interrupt 7.5.3 Operation When the CPU fetches and executes the software interrupt instruction, the software interrupt processing microcode is activated. The software interrupt processing microcode saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. The microcode then fetches three bytes of interrupt vector and loads them onto PC and PCB, resets the I flag, and sets the S flag.
7.6 Extended intelligent I/O service (EI2OS) 7.6 Extended intelligent I/O service (EI 7.6.1 Overview OS is a type of hardware interrupt operation that automatically transfers data between I/O and memory. Conventionally, data is transferred between I/O and memory by an interrupt processing program. EI however, enables data to be transferred as if in DMA mode.
7.6 Extended intelligent I/O service (EI2OS) 7.6.2 Structure OS is handled by the following four sections: Internal resources ....Interrupt enable and request bits: Used to control interrupt requests from resources. Interrupt controller ICR:Assigns interrupt levels, determines the priority levels of simultaneously requested interrupts, and selects the OS operation.
7.6 Extended intelligent I/O service (EI2OS) [bits 15 to 12] or [bits 7 to 4] ICS3 to ICS0 These bits are used to select the EI OS channel. These bits are write-only. The value specified in these bits determines the address of the extended intelligent I/O service descriptor in memory, which is explained later.
7.6 Extended intelligent I/O service (EI2OS) [bit 11] or [bit 3] ISE This is the EI OS enable bit. This bit can be read or written to. Upon issuance of an interrupt request, OS is activated if this bit is set to ’1’ and the interrupt sequence is activated if this bit is set to ’0.’ If the EI OS end condition is satisfied (the S1 and S0 bits are not ’00’), the ISE bit is cleared to ’0.’...
7.6 Extended intelligent I/O service (EI2OS) (2)Extended intelligent I/O service descriptor (ISD) The extended intelligent I/O service descriptor exists between 000100 and 00017F in internal RAM, and consists of the following items: Data transfer control data Status data Buffer address pointer Figure 7.6.2a shows the configuration of the extended intelligent I/O service descriptor.
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7.6 Extended intelligent I/O service (EI2OS) I/O register address pointer (IOA) This is a 16-bit register that indicates the low-order address (A15 to A0) of the buffer and I/O register used for data transfer to and from the buffer. The high-order address (A23 to A16) are all zeroes, and any I/O between addresses 000000 and 00FFFF can be specified.
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7.6 Extended intelligent I/O service (EI2OS) [bit 1] DIR: Specify the data transfer direction. I/O → Buffer Buffer → I/O [bit 0] SE: Control the termination of the extended intelligent I/O service based on resource requests. The extended intelligent I/O service is not terminated by a resource request.
7.6 Extended intelligent I/O service (EI2OS) 7.6.3 Operation Buffer address pointer I/OA I/O address pointer OS descriptor ISCS OS status Data counter OS enable bit Interrupt request issued S1 and S0 : OS end status from internal resource ISE = 1 Interrupt sequence Reading ISD/ISCS End request from resource...
7.6 Extended intelligent I/O service (EI2OS) Processing by CPU Processing by EI2OS OS initialization Normal (Interrupt request) termination AND (ISE = 1) JOB execution Data transfer Re-setting of extended intelligent I/O service (Switching channels) Processing data in buffer Figure 7.6.3b EI OS use flow Chapter 7: Interrupt MB90580 Series...
7.6 Extended intelligent I/O service (EI2OS) 7.6.4 EI OS Execution Time (1) When data transfer continues (when the stop condition is not satisfied) EI2OS Execution Time = (value in Table 7.6.4a + value in Table 7.6.4b) machine cycle Table 7.6.4a Execution time when the extended I2OS continues ISCS SE bit Set to ’0’...
Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation. Fujitsu recommends using exception processing only for debugging or for activating emergency recovery software.
Chapter 8: Parallel Ports 8.1 Outline In MB90580 series, there are 10 parallel ports which are as follows: • Port 0 (8 CMOS I/O pins) • Port 1 (8 CMOS I/O pins) • Port 2 (8 CMOS I/O pins) • Port 3 (8 CMOS I/O pins) •...
8.2 Block Diagram 8.2 Block Diagram Internal data bus Data register read Data register Data register write Direction register Direction register write Direction register read Figure 8.2a Block diagram of I/O port Internal data bus Pull-up resistor (about 50 kΩ) Data register Direction register Resistor register...
8.3 Registers and register details 8.3.3 Output pin register Port 4 pin register Bit number Address : 00001B OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 ODR4 Read/write Initial value This register controls the open drain in output mode. Standard output port in output mode [initial value] Open drain output port in output mode Note: This register is not used in input mode.
8.3 Registers and register details 8.3.5 Analogue Input Enable Register Port 5 analogue enable register Bit number Address : 00001C ADER ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Read/write Initial value This register controls the .behaviour of port 5. Port input mode Analogue input mode [initial value]...
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8.3 Registers and register details [bit 9] - LN9 controls Port 9 Normal output buffer [initial value] Low noise output buffer [bit 8] - LN8 controls Port 8 Normal output buffer [initial value] Low noise output buffer [bit 7] - LN7 controls Port 7 Normal output buffer [initial value] Low noise output buffer...
Chapter 9: DTP/External Interrupt 9.1 Outline The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the MC-16LX CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes requests to the F MC-16LX CPU to activate the extended intelligent I/O service (EI OS) or interrupt processing.
9.3 Registers and Register Details 9.3.2 Interrupt/DTP cause register (EIRR: External interrupt request register) Interrupt/DTP cause register Bit number Address : 000031 EIRR Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value When read, EIRR indicates the current external interrupt/DTP requests. When written, EIRR clears the flip-flop values indicating those requests.
9.4 Operations 9.4 Operations 9.4.1 External interrupts Once an external interrupt request is set, this resource issues an interrupt request signal to the interrupt controller when a request specified by the ELVR register is input to the corresponding pin. The interrupt controller identifies the priority levels of the simultaneous interrupts, and issues an interrupt request to the MC-16 CPU if the interrupt from this resource has the highest priority level.
9.4 Operations 9.4.2 DTP operation To activate the intelligent I/O service, the user program initially sets the address of a register, assigned between 000000 and 0000FF , in the I/O address pointer of the intelligent I/O service descriptor. Then, the user program sets the start address of the memory buffer in the buffer address pointer. The DTP operation sequence is almost the same as for external interrupts.
9.4 Operations 9.4.3 Switching between external interrupt and DTP requests To switch between external interrupt and DTP requests, use the ISE bit in the ICR register corresponding to this resource, which is in the interrupt controller. Each pin is individually assigned ICR. Thus, a pin is used for a DTP request if ’1’...
9.5 Notes on use 9.5 Notes on use 9.5.1 Conditions on the externally connected peripheral when DTP is used DTP supports only external peripherals that automatically clear a request once a transfer is completed. The system must be designed so that a transfer request is canceled within three machine cycles (provisional) after transfer operation starts.
Chapter 10: Delayed Interrupt Generation Module 10.1 Outline The delayed interrupt generation module generates interrupts for switching tasks for development on a real-time operating system (REALOS series). The module can be used to generate softwarewise generates hardware interrupt requests to the CPU and cancel the interrupts. This module does not conform to the extended intelligent I/O service (EI OS).
10.4 Operations 10.4 Operations 10.4.1 Delayed interrupt occurrence When the CPU writes ’1’ to the relevant bit of DIRR by software, the request latch in the delayed interrupt source module is set and an interrupt request is issued to the interrupt controller. If this interrupt has the highest priority or if there is no other interrupt request, the interrupt controller issues an interrupt request to the F MC-16 CPU.
Chapter 11: Communication Prescaler 11.1 Outline The operation clock for the UART is obtained by dividing the machine clock. UART is designed so that a constant baud rate can be obtained for a variety of machine clocks by the user of the communication prescaler.
11.4 Operations 11.4 Operations Depending on the machine clock φ to be used, the communication prescaler register should be set as follows. For details please refer to Chapter 12, UART. φ φ machine clock DIV3 DIV2 DIV1 DIV0 /div 4 MHz 6 MHz 1 MHz 8 MHz...
12.3 Register and Register Details 12.3.1 Serial Mode Register (SMR0/1/2/3/4) Serial mode register Address : 000020 Bit number 000024 000028 SMR0 Reserved SCKE 000088 SMR1 000082 SMR2 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) SMR3 Initial value SMR4 The SMR register specifies the UART operation mode.
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12.3 Register and Register Details [bit 1] SCKE (SCLK enable): This bit is used to specify whether to use the SCK0 pin as a clock input pin or clock output pin in CLK synchronous mode (mode 2) communication. Set ’0’ in this bit in CLK asynchronous mode or external clock mode. The SCK0 pin is used as a clock input pin.
12.3 Register and Register Details 12.3.2 Serial Control Register (SCR0/1/2/3/4) Serial control register Address : 000021 Bit number 000025 000029 SCR0 000083 SCR1 000089 SCR2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write SCR3 SCR4 Initial value The SCR register controls the transfer protocol for serial communications. [bit 15] PEN (Parity enable): This bit is used to specify whether to perform serial data communication using a parity bit.
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12.3 Register and Register Details [bit 11> A/D (Address/data): This bit is used to specify the data format of the frame to be sent or received in multi-processor asyn- chronous communication mode (mode 1). Data frame [initial value] Address frame [bit 10] REC (Receiver error clear): This bit is used to clear the SSR register error flags (PE, ORE, and FRE).
12.3 Register and Register Details 12.3.3 Serial Input Data Register (SIDR0/1/2/3/4)/ Serial Ouput Data Register (SODR0/1/2/3/4) Serial input register/Serial output register Address : 000022 Bit number 000026 00002A SIDR0/SODR0 000084 SIDR1/SODR1 00008A SIDR2/SODR2 SIDR3/SODR3 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
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12.3 Register and Register Details [bit 13] FRE (Framing error) This interrupt request flag is set when a framing error occurs during reception. To clear a set flag, write ’0’ to the REC bit (bit 10) of the SCR register. When this bit is set, the data in SIDR is invalid.
12.4 Operations 12.4 Operations 12.4.1 Operation modes Table 12.4.1a lists the operation modes of UART. The modes can be switched by setting a value in the SMR or SCR register. Table 12.4.1a UART operation modes Data Mode Parity Operation mode Stop bit length length Yes/No...
12.4 Operations (2) Internal timer When ’110’ is set in CS2 to CS0 and an internal timer is selected, the 16-bit timer (timer 0) is used in reload mode. The baud rate is calculated as described below in this case: (∅÷N)/(16 ×...
12.4 Operations 12.4.3 Asynchronous mode (1) Transfer data format UART handles NRX (non return to zero) format data only. Figure 12.4.3a gives the data format. SIN0, SOT0 (Mode 0) Start LSB MSB Stop (Mode 1) A/D Stop 01001101 is transferred. Figure 12.4.3a Transfer data format (modes 0 and 1) As shown in Figure 12.4.3a, the transfer data always starts from the start bit (’L’...
12.4 Operations 12.4.4 CLK synchronous mode (1) Transfer data format UART handles NRX (non return to zero) format data only. Figure 12.4.4a shows the transmission/reception clock and data. SODR write Mark SCLK RXE, TXE SIN0, SOT0 (Mode 2) 01001101 is transferred. Figure 12.4.4a Transfer data format (mode 2) When the internal clock (dedicated baud rate generator or internal timer) is selected, a data reception synchronization clock is automatically generated upon data transmission.
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12.4 Operations (3) Start of communication Communication is started by writing data in the SODR register. Virtual transmission data must be writ- ten to the SODR register even when only reception is to be performed. (4) End of communication The end of communication can be checked by ’1’ written to the RDRF flag of the SSR register. Use the ORE bit of the SSR register to check whether communication has been successful.
12.4 Operations 12.4.5 Interrupt occurrence and flag set timing UART has five flags and two interrupt causes. The five flags are PE, ORE, FRE, RDRF, and TDRE. PE indicates a parity error, ORE indicates an overrun error, and FRE indicates a framing error. These three flags are set when the corresponding error occurs during reception, and are cleared when ’0’...
12.4 Operations Then, an interrupt request is issued to the CPU. If the ORE flag is active, the data in SIDR is invalid. Data RDRF Reception interrupt Figure 12.4.5c Timing to set ORE and RDRF (mode 2) (4) Transmission in modes 0, 1, and 2 TDRE is cleared when a data item is written into the SODR register.
12.4 Operations 12.4.6 I OS (Intelligent I/O service) For I OS, see the section describing I 12.4.7 Notes on use To set a communication mode, ensure that UART is not in operation. The data sent or received during mode setting is not guaranteed. 12.4.8 Application Mode 1 is used when two or more slave CPUs are connected to a single host CPU (see Figure 12.4.8a).
12.4 Operations (Host CPU) START Select transfer mode 1. Set the data for selecting the slave CPUs in D0 to D7 and set ’1’ in A/D to transfer one byte. Set ’0’ in A/D. Reception is enabled. Communication with the slave CPU End communication? Communicate with other slave CPU?
Chapter 13: IE Bus 13.1 Outline IEBus (Inter Equipment Bus) is a small-scale two-line serial bus interface intended to transfer data between equipment and equipment. It is designed for use in automotive and general industrial applications. The communication protocol of the IEBus has the following features: •...
13.3 Registers and Register Details Mutliaddress, control bit set register (DCWR) Bit Number Address: 000075 DCWR Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value Telegraph length set register (DEWR) Bit Number Address: 000074 DECR Read/write (R/W) (R/W) (R/W) (R/W) (R/W)
13.3 Registers and Register Details [bit 11] TIE (Transmit interrupt enable): This bit controls transmit interrupt as described below. Transmit interrupt disabled Transmit interrupt enabled The transmit interrupt is occurred under the following condition: • In master transmit, after master address field has been transmitted, the master unit has won in arbitration.
13.3 Registers and Register Details [bit 3, 2] CS1, CS0 (Cycle select): These bits control both the CPU internal clock cycle and IEBUS controller clock cycle and CS1 and CS0 must be set to ‘0’. . Table 13.3.2d Internal clock frequency CPU internal clock φ...
13.3 Registers and Register Details 13.3.5 Mutliaddress, control bit set register (DCWR) Mutliaddress, control bit set register (DCWR) Bit Number Address: 000075 DCWR Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value [bit 15, 14, 13, 12] DO3, DO2, DO1, DO0 (Multiaddress/normal communication select bits): These bits are used to select multiaddress (more than one slave) or normal communication (one slave).
13.3 Registers and Register Details 13.3.6 Telegraph length set register (DEWR) Telegraph length set register (DEWR) Bit Number Address: 000074 DECR Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value This register is used to set the number of data bytes to be transmitted and is valid only for data transmission.
13.3 Registers and Register Details 13.3.7 Status register upper byte (STRH) Status register upper byte (STRH) Bit Number Address: 000079 STRH Read/write (R/W) (R/W) (R/W) Initial value [bit 15] COM (Communication status): This bit indicates the communication status as described below. Communication is prohibited Communication is enabled When this bit is ‘0’...
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13.3 Registers and Register Details [bit 11] RIF (Receive interrupt flag): This bit is set when receive interrupt is occurred. No receive interrupt request Have receive interrupt request This bit is cleared by writing ‘0’ to this bit or after the extended intelligent I/O service has been served. This bit is written ‘0’...
13.3 Registers and Register Details 13.3.8 Status register lower byte (STRL) Status register lower byte (STRL) Bit Number Address: 000078 WDBF RDBF WDBE RDBE STRL Read/write Initial value [bit 7] WDBF (Write data buffer full): This flag indicates the status of the write data buffer (WDB). Write data buffer is not full Write data buffer is full This bit is set when WDB is full and cleared when at least one byte of data can be written into WDB.
13.3 Registers and Register Details [bit 3-0] ST3, ST2, ST1, ST0 (Operation status bits) These bits indicates the communication status of the unit and generates the corresponding interrupt during transmission or reception. By reading these bits, the communication status of the unit can be known.
13.3 Registers and Register Details 13.3.11 Multiaddress, control bit read register (DCRR) Multiaddress, control bit read register (DCRR) Bit Number Address: 00007F DCRR Read/write Initial value [bit 15-12] DO3, DO2, DO1, DO0 (Multiaddress/normal communication bits): In slave mode, the received multiaddress bit from the master is stored in bit DO0. If the unit itself is the master, the multiaddress/normal communication set bits (DO3-0) in multiaddress, control bit set register (DCWR) is read out.
13.3 Registers and Register Details 13.3.12 Telegraph length read register (DERR) Telegraph length read register (DERR) Bit Number Address: 00007E DERR Read/write Initial value if the unit itself is the receiver, this register stores the number of data specified by telegraph length field. If the unit itself is the transmitter, the telegraph length bits in telegraph length set register (DEWR) are read.
13.3 Registers and Register Details 13.3.13 Read data buffer (RDB) Read data buffer (RDB) Bit Number Address: 000081 Read/write Initial value This register (internally is a 8-byte FIFO buffer) stores received data in data field of the communication frame. When eight byte data have been received, RDB becomes full and receive interrupt is generated. Then data in RDB should be read out before the next coming byte of data is received as shown in Table 13.3.13a .
13.3 Registers and Register Details 13.3.14 Write data buffer (WDB) Write data buffer (WDB) Bit Number Address: 000080 Read/write Initial value This register (internally is a 8-byte FIFO buffer) stored data to be transmitted in data field of the communication frame. The data write interrupt timing is set by the two bits TIT1, TIT0 in command register (CMRL).
13.4 IEBus Communication Protocol 13.4 IEBus Communication Protocol 13.4.1 Overview IEBus (Inter Equipment Bus) is a small-scale two-line serial bus interface intended to transfer data between equipment and equipment. • Communication method Data are transferred by means of half duplex asynchronous communication. •...
13.4 IEBus Communication Protocol 13.4.2 Determining bus mastership (arbitration) The equipment connected to the IEBus performs an operation to occupy the bus when it controls another equipment. This operation is called arbitration. Arbitration is to grant the bus mastership to one of several units that have simultaneously started transmission.
13.4 IEBus Communication Protocol 13.4.4 Communication address In IEBus, each equipment is assigned to a specific 12-bit communication address. The communication address is consisted of: Higher 4 bits:group number (identify which group the equipment belongs to) Lower 8 bits:unit number (identify each equipment in one group) 13.4.5 Multiaddress communication In normal communication mode, the communication is performed on a one-to-one basis, i.e.
13.4 IEBus Communication Protocol 13.4.6 Transfer protocol The signal transmit format of the IEBus is shown as below Master Telegraph Field Name Slave address Control field Data field Header address field length field field No. of bits 8 1 1 Master Slave Telegraph...
13.4 IEBus Communication Protocol (3) Slave address field This field outputs the address of the other unit with which the master is to communicate and is consisted of 12 bits of slave address with MSB transmitting first, parity bit and acknowledge bit. After a 12-bit slave address has been transmitted, a parity bit is output to ensure that the slave address is not received by mistake.
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13.4 IEBus Communication Protocol case, the second and following communication frames will transmit the remaining data bytes specified in the telegraph length field. The function of telegraph length field differs when the master is in transmit mode (bit 3 of control bits is ‘1’) or receive mode (bit 3 of control bits is ‘0’) as follow: •...
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13.4 IEBus Communication Protocol • At the end of data field The acknowledge bit is defined as: ‘0’: The transmit data is recognized (ACK) ‘1’: The transmit data is not recognized (NAK) The acknowledge bit is ignored in multiaddress communication. 1.
13.4 IEBus Communication Protocol 13.4.7 Transmit data The content in data field is controlled by the control bits in control field and is shown below: Table 13.4.7a Control bits setting Note Note 2 Bit 3 Function Bit 2 Bit 1 Bit 0 Slave status (SSR) read Undefined...
13.4 IEBus Communication Protocol (1) Slave status (SSR) read (control bits: 0H, 6H) By reading the slave status, the master can understand why the slave has not returned the acknowledge bit (ACK). The slave status is determined in respect to the result of the last communication performed by the slave unit.
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13.4 IEBus Communication Protocol (3) Read lock address (control bits: 4H, 5H) When the lock address is read (control bits: 4H, 5H), the address (12-bit) of the master that has issued the lock instruction is configured in 1-byte units as shown below and is read. Control bits: 4H Lower 8 bits Control bits: 5H...
13.4 IEBus Communication Protocol 13.4.8 Bit format The format of the bits constituting an IEBus communication frame is shown below: Logic ‘1’ Logic ‘0’ Synchronizatio Data Pause Synchronizatio Data Preparation period period period period period period Logic ‘1’: voltage difference between inter-bus wires (BUS+ and BUS-)is below 20 mV (low level) Logic ‘0’: voltage difference between inter-bus wires (BUS+ and BUS-) is above 120 mV (high level) Preparation period: First low-level period (logic ‘1’) Synchronization period: Next high-level period (logic ‘0’)
13.5 Operation 13.5 Operation 13.5.1 IEBus control (1) Master transmit The unit is set as master transmit to transmit data to the slave by sending data/command control bits as AH, BH, EH or FH. The sequences for operating in master transmit are described as below: 1.
13.5 Operation 5. If error occurs during transmission or in multi-frame communication the number of data byte specified in DEWR cannot be transmitted completely, the state code (3H) indicating transmission terminated without all data transmitted is set in STRL:ST3-0. Transmit interrupt will occur. At this time, the content of communication error can be known by checking the status of TSL, PEF, TE in status register (STRH).
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13.5 Operation (4) Slave receive This mode is set when the slave unit receive control bits AH, BH, EH or FH from the master. The sequences for operating as slave receive are described as below: 1. After the slave returns the acknowledge bit in telegraph length field, the number of receive data byte is written in the telegraph length read register (DERR).
13.5 Operation 13.5.2 Communication status In the status register, there are four bits ST3-0 indicating the status code. After the status code has been set, interrupt request is generated. During the interrupt routine, the communication status can be investigated by reading the status register. But at the beginning of master, slave and multiaddress receive, no interrupt will be generated (1) Master, slave data transmit (transmit interrupt occurs) When the unit won the arbitration in multiaddress or master address field, it becomes master unit.
13.5 Operation (3) Slave receive (receive interrupt occurs) When data/command is received from the master unit, the status code ST3-0 is set and shown as below: Table 13.5.2c Meaning of status code ST3-0 for slave receive Code Name Code ST3-0 Content Indicates that the slave unit has received the telegraph field correctly from Slave receive...
13.5 Operation 13.5.3 Program flow example for IEBus controller (1) Main routine Begin IEBus initial setup Enable IEBus controller IEBus controller operates (2) Interrupt routine This routine is executed when start of transmission or end of reception. In interrupt routine, the status code (ST3-0) in status register STRL is read, then the transmit data can be written or receive data can be read.
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13.5 Operation (3) IEBus initial setup The initial setup sequence includes setting its unit address, the command register and releasing the communication inhibit state. If the unit is not set as master, there is no need to set the slave address in slave address register.
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13.5 Operation (4) Master transmit routine After the communication inhibit state is released, the unit won the arbitration and acts as master. Then master transmit routine is used to transmit data to the slave. This routine is executed inside interrupt routine with ST3-0 bits (upper 2 bits are 00) in status register indicating the status as master transmit has been set.
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13.5 Operation (5) Slave transmit routine After the slave receives the control bits and is set as slave transmit, this routine is used to transmit data to the master. This routine is executed inside interrupt routine with ST3-0 bits (upper 2 bits are 00) in status register indicating the status as slave transmit has been set.
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13.5 Operation (6) Master receive routine After the master transmit the control bits, this routine is used for the master to receive data, slave address or log address from the slave. This routine is consisted of four parts depending on the content of ST3-0. 1.
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13.5 Operation 3. Master receive ends normally (ST3-0 is 6H) Begin Note1 Read out multiaddress, control bits Read multiaddress, control bits and telegraph length bits and master receive byte number Done by hardware number of master receive data byte RDB read Read out master receive data N - 1 Done by hardware...
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13.5 Operation 4. Master reception ends without all data being received (ST3-0 is 7H) Begin Note1 Read out multiaddress, control bits Read multiaddress, control and master receive byte number bits and telegraph length bits Done by hardware number of master receive data byte STRH/L read Note2 RDBE = 1?
13.5 Operation 13.5.4 Timing Diagram of Multiple Frame Transmission 1. When setting ‘1’ on WDBC (Master side of master transmission) Frist Frame Second Frame DataN-3(04H) DataN-2(03H) Start Multi-Add Master- Add Slave-Add Control Telegraph bytes DataN-1(FFH) DataN(FEH) Can read the rest of the transmission byte Transmission data left is 0 DERR Read...
13.5 Operation 2. When setting ‘0’ on WDBC (Master side of master transmission) Frist Frame Second Frame DataN-3(04H) Master- Add Slave-Add DataN-2(03H) Start Multi-Add Control Telegraph bytes DataN-1(02H) DataN(01H) Can read the rest of the transmission bytes Transmission data left is 0 DERR Read DEER...
13.5 Operation 13.5.5 Timing diaram of transmission data when an error is generated 1. The following is an example when the master transmission, an error is generated at the second byte data on the slave side. NAK is received by the master. the following data is transmitted at the second frame.
13.5 Operation 2. The following is an example when the master transmission, an error is generated at the second byte data on the master side. The following data is transmitted at the second frame. Slave reception movements until the figure becomes the maximum transmission byte Header Data Filed...
Chapter 14: 8/16-Bit PPG 14.1 Outline The 8/16-bit PPG timer is an 8-bit reload timer module, and outputs PPG by control pulse output according to timer operation. The hardware includes two eight-bit down counters, four eight-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs.
14.3 Registers and Register Details 14.3.1 PPG0 operation mode control register (PPGC0) PPG0 operation mode control register Bit No. Address: ch0 000044H PEN0 PE00 PIE0 PUF0 Reserved PPGC0 Read/write (R/W) (R/W) (R/W) (R/W) Initial value PPGC0 is a five-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers.
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14.3 Registers and Register Details This bit controls the PPG counter underflow as described below. PUF0 Operation PPG counter underflow is not detected [initial value] PPG counter underflow is detected In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, ’1’ is written to this bit when an underflow occurs as a result of the ch0 counter value becoming between 00H and FFH.
14.3 Registers and Register Details 14.3.2 PPG1 operation mode control register (PPGC1) PPG1 operation mode control register Bit No. Address: ch0 000045H PEN1 PE10 PIE1 PUF1 MD1 MD0 Reserved PPGC1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write Initial value PPGC0 is a seven-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers.
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14.3 Registers and Register Details [bit 11] PUF1 (PPG underflow flag): PPG counter underflow bit This bit controls the PPG counter underflow as described below. PUF1 Operation PPG counter underflow is not detected [initial value] PPG counter underflow is detected In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, ’1’...
14.3 Registers and Register Details 14.3.3 PPG0, 1 output pin control register (PPGOE) PPG0,1 output control register Bit No. Reserved Reserved PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PPGOE Address: ch0 1 0046H Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value This is an 8-bit control register that controls the pin output of this block.
14.4 Operations 14.4 Operations This block has two channels of 8-bit PPG units. These two channels can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode. Each of the 8-bit PPG units has two eight-bit reload registers. One reload register is for the L side (PRLL) and the other is for the H side (PRLH).
14.4 Operations (2) PPG output operation In this block, the ch0 PPG is activated to start counting when ’1’ is written to bit 7 (PEN0) of the PPGC0 (PWM operation mode control) register. Similarly, the ch1 PPG is activated to start counting when ’1’ is written to bit 15 (PEN1) of the PPGC1 register.
14.4 Operations (4) Count clock selection The count clock used for the operation of this block is supplied from a peripheral clock or time base counter. The count clock can be selected from six types. Select ch0 clock at bit 4 to 2 (PCM2 to 0) of the PPGOE register, and ch1 clock at bit 7 to S (PCS2 to 0) of the PPGOE register.
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14.4 Operations (6) Interrupts For this module, an interrupt becomes active when the reload value is counted out and a borrow occurs. In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by a borrow in each counter.
14.4 Operations (8) Reload register write timing In a mode other than 16-bit PPG mode, it is recommended to use a word transfer instruction to write data in reload registers PRLL and PRLH. If two byte transfer instructions are used to write a data item to these registers, a pulse of unexpected width may be output depending on the timing.
Chapter 15: 16-Bit Reload Timer (with Event Count Function) 15.1 Outline The 16-bit reload timer 1 consists of a 16-bit down-counter, a 16-bit reload register, one input pin (TIN) and one output pin (TOUT), and a control register. It has an internal clock mode for counting down in synchronization to three types of internal clocks and an event count mode for counting down detecting a given edge of the pulse input to the external bus pin, and either of the two functions can be selectively used.
15.3 Registers and Register Details 15.3.1 Timer control status register (TMCSR) Timer control status register (upper) Bit number Address: ch0 000049 TMCSR0-2 ch1 00004D — — — — CSL1 CSL0 MOD2 MOD1 (HIGH) ch2 000051 Read/write — —...
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15.3 Registers and Register Details [Bits 9, 8, 7] MOD2, MOD1, MOD0 These bits set the operation mode and I/O pin functions. The MOD2 bit selects the I/O functions. When MOD2 = “0”, the input pin functions as a trigger input. In this case, the reload register contents is loaded to the counter when an active edge is input to the input pin and count operation proceeds.
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15.3 Registers and Register Details [Bit 4] RELD (Reload) This bit enables reload operations. When RELD is “1”, the timer operates in reload mode. In this mode, the timer loads the reload register contents into the counter and continues counting whenever an underflow occurs (when the counter value changes from 0000 to FFFF ).
15.4 Operation 15.4 Operation 15.4.1 Internal clock operation The machine clock divided by 2 , or 2 can be selected as the clock sources for operating the timer from an internal divide clock. The external input pin can be selected as either a trigger input or gate input by a register setting.
15.4 Operation 15.4.2 Underflow operation An underflow is defined for this timer as the time when the counter value changes from 0000 to FFFF Therefore, an underflow occurs after (reload register setting + 1) counts. If the RELD bit in the control register is “1” when the underflow occurs, the contents of the reload register is loaded into the counter and counting continues.
15.4 Operation 15.4.3 Input pin functions (for internal clock mode) The TIN pin can be used as either a trigger input or a gate input when an internal clock is selected as the clock source. When used as a trigger input, input of an active edge causes the timer to load the reload register contents to the counter and then start count operation after clearing the internal prescaler.
15.4 Operation 15.4.5 Output pin functions In reload mode, the TOUT pin performs toggle output (inverts at each underflow). In one-shot mode, the TOUT pin functions as a pulse output that outputs a particular level while the count is in progress. The OUTL bit of the control register sets the output polarity.
15.4.7 Counter operation state The counter state is determined by the CNTE bit in the control register and the internal WAIT signal. Avail- able states are: CNTE = “0” and WAIT = “1” (STOP state), CNTE = “1” and WAIT = “1” (WAIT state for trig- ger), and CNTE = “1”...
Chapter 16: A/D Converter 16.1 Outline The A/D converter converts analog input voltages into digital values. The A/D converter has the following features: Conversion time: 5.2 µs min. per channel (at 16 MHz machine clock) • • RC sequential compare conversion format with sample and hold circuit •...
16.3 Registers and Register Details 16.3 Registers and Register Details Control Status Registers (Upper Byte) Bit number Address : 000037 BUSY INTE PAUS STS1 STS0 STRT ADCS2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write Initial value Control Status Registers (Lower Byte) Bit number Address : 000036 ANS2...
16.3 Registers and Register Details 16.3.1 Control status registers (ADCS1 and ADCS2) These registers are used to control the A/D converter and display the status. Control Status Registers (Upper Byte) Bit number Address : 000037 BUSY INTE PAUS STS1 STS0 STRT ADCS2 (R/W) (R/W)
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16.3 Registers and Register Details [bit 12] PAUS (A/D conversion pause): This bit is set when the A/D conversion is paused. Only one register is available for storing the A/D conversion result. Therefore, unless the conversion results are transferred by I2OS, the result data would be continuously updated and destroyed in contin- uous conversion.
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16.3 Registers and Register Details [bits 7 and 6] MD1 and MD0 (A/D converter mode set): These bits are used to set the A/D converter operation mode. Operation mode Single mode. Reactivation during operation is allowed. Single mode. Reactivation during operation is not allowed. Continuous mode.
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16.3 Registers and Register Details [bits 2, 1, and 0] ANE2, ANE1, and ANE0 (Analog end channel set): Use these bits to set the A/D conversion end channel. ANE2 ANE1 ANE0 End channel * When the same channel is written to ANE2 to ANE0 and ANS2 to ANS0, conversion is performed for one channel only (single conversion).
16.3 Registers and Register Details 16.3.2 ADCR1 and ADCR0 (Data registers) Data Registers (Upper Byte) Bit number Address : 000039 Reserved ADCR2 Read/write Initial value Data Registers (Lower Byte) Bit number Address : 000038 ADCR1 Read/write Initial value Figure 16.3.2a Data Registers [bit 15] This is reserved bit.
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16.3 Registers and Register Details [bit 12, 11] : CT1, CT0 (Compare Time) These bits is used for setting the comparsion time in terms of machine cycle. Comparsion time machine cycle Comparsion time 176 machine cycle 22ms at 8MHz machine clock 22ms at 16MHz machine 352 machine cycle clock...
16.4 Operations 16.4 Operations The A/D converter operates in the sequential compare format, and has a 8-bit resolution. Since the A/D converter has only one register (8 bits) for storing the conversion result, the conversion data registers (ADCR0) are updated each time conversion is completed. Thus, the A/D converter must not be used alone for continuous conversion.
16.4 Operations (3) Stop mode In this mode, the converter sequentially converts the analog inputs specified with the ANS and ANE bits, pausing each time conversion for one channel is completed. To release pausing, activate the A/D converter again. After the conversion is completed for the end channel specified with the ANE bits, conversion is repeated from the analog inputs of the ANS.
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16.4 Operations Usage Starting I OS in single mode •To terminate conversion after analog inputs AN1 to AN3 are converted •To transfer conversion data sequentially to addresses 200H to 206H •To start conversion by software •To use the highest interrupt level OS setting ICR3 #08H...
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16.4 Operations Usage Starting I OS in continuous mode •To convert analog inputs AN3 to AN5 and obtain two conversion data items for each channel •To transfer conversion data sequentially to addresses 600H to 60CH • •To start conversion by external edge input To use the highest interrupt level OS setting ICR3...
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16.4 Operations Usage Starting I OS in stop mode •To convert analog input AN3 12 times at fixed intervals •To transfer conversion data sequentially to addresses 600H to 618H • •To start conversion by external edge input To use the highest interrupt level OS setting ICR3 #08H...
16.4 Operations (5) Conversion data protection The A/D converter has a conversion data protection function that enables continuous conversion and preservation of multiple data items using I Since there is only one conversion data register, its value is updated each time conversion is com- pleted.
16.5 Notes on use 16.5 Notes on use To start the A/D converter upon an external trigger or internal timer, A/D activation factor bits STS1 and STS0 of the ADCS2 register are used. Ensure that the input values of the external trigger or internal timer are inactive.
Chapter 17: D/A Converter 17.1 Outline This is an R-2R format D/A converter, having an eight-bit resolution. The D/A converter has two channels. Output control can be performed independently for the two channels using the D/A control register.
17.4 Operations 17.4 Operations D/A output is started by writing a desired D/A output value to the D/A data register (DADR) and setting ’1’ to the enable bit for the corresponding D/A output channel in the D/A control register (DACR). Disabling D/A output turns off the analog switch that is inserted serially into the output of each D/A con- verter channel.
Chapter 18: Pulse Width Counter (PWC) Timer 18.1 Outline This module is a multi-function 16-bit up-counter with a reload function and a function for counting pulse widths on the input signal. The module hardware consists of a 16-bit up-counter, input pulse divider, divide ratio control register, four count input pins, one pulse output pin, and a 16-bit control register.
18.3 Regiaters and Register Details 18.3 Regiaters and Register Details PWC Control Status Register (Upper Byte) Bit number Address : 000055 PWCSR STRT STOP EDIR EDIE OVIR OVIE POUT (HIGH) Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value PWC Control Status Register (Lower Byte) Bit number Address : 000054 CSK1...
18.3 Regiaters and Register Details 18.3.1 PWC control status register (PWCSR) PWC Control Status Register (Upper Byte) Bit number Address : 000055 PWCSR STRT STOP EDIR EDIE OVIR OVIE POUT (HIGH) Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value PWC Control Status Register (Lower Byte) Bit number Address : 000054...
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18.3 Regiaters and Register Details [bit 13] EDIR (End interrupt request) This flag indicates when counting ends in pulse width count mode. A count end interrupt request is generated if the interrupt is enabled (bit 12: EDIE = "1") when this bit is set. Set timing Set when pulse width counting ends (when the count result is placed in PWCR).
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18.3 Regiaters and Register Details [bit 9] ERR (Error) This flag is used when continuous counting is performed in pulse width count mode. The flag indicates that the next count has completed before the previous count result has been read from PWCR.
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18.3 Regiaters and Register Details [bits 5, 4] PIS1, PIS0 (Pulse input select) These bits select the input pin on which to perform pulse width counting. PIS1 PIS0 Count Input Pin Selection Always set this value. (Initial value) Setting unavailable (Do not set any of these values.) After a reset: Initialized to "00 ".
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18.3 Regiaters and Register Details [bits 2, 1, 0] MOD2, MOD1, MOD0 (MOD2, 1, 0) These bits select the operation mode and the pulse edges for width counting. MOD2 MOD1 MOD0 Operation Mode/Count Edge Selection Timer mode, no pulse output (Initial value) Timer mode, pulse output enabled (using the POT pin): Reload mode only Inter-edge pulse width count mode ( ⇑...
18.3 Regiaters and Register Details 18.3.3 Divide Ratio Control Register (DIVR) Divide Ratio Control Register Bit number Address : 000058 — — — — — — DIV1 DIV0 DIVR Read/write (R/W) (R/W) Initial value This register is only used in divided period count mode (bits 2, 1, 0: MOD2, 1, 0 of PWCSR = "011"). In divided period count mode, pulses input from the count pin are divided by the divide ratio set in this register and the period of the divided signal is measured.
18.3 Regiaters and Register Details 18.3.4 PWC noise cancelling register (RNCR) PWC Noise Cancelling register Bit number Address : 000086 — — — — — RNCR Read/write (R/W) (R/W) (R/W) Initial value The PWC noise removal circuit is used for removing noises form the input signal. H level and L level detection will be applied to the input signal after it was ‘cleaned’...
18.4 Operations 18.4 Operations (1) Summary of Operation This block is a multi-function timer based on a 16-bit up-count timer and incorporating a count input pin and 8-bit input divider. The block has two main functions: a timer function and a pulse width count function.
18.4 Operations (2) Pulse Width Count Function This function counts the time period between specified events on an input pulse. After the function is activated, the count does not start until the specified count start edge is input. The counter is cleared to "0000 "...
18.4 Operations (3) Count Clock Selection The timer count clock can be selected from three internal clock sources. The available clock sources are listed below. Table 18.4a Count Clock Selection PWCSR/bit7, 6:CKS1, 0 Selected Internal Count Clock Machine cycle divided by 4 (0.25µs for a 16MHz machine cycle) (Initial value) Machine cycle divided by 16 (1.0µs for a 16MHz machine cycle)
18.4 Operations (4) Operation Mode Selection The operation mode and count mode are selected by PWCSR settings. • Operation mode setting PWCSR bits 2, 1, and 0: Bits MOD2, MOD1, and MOD0 (Selects timer or pulse width count mode and specifies which edges control counting.) •...
18.4 Operations (5) Starting and Stopping the Timer and Pulse Width Count Starting, restarting, and forcibly halting each operation is performed using bits 15 and 14 (STRT and STOP) of PWCSR. Writing "0" to the STRT bit starts or restarts operation and writing "0" to the STOP bit forcibly halts operation.
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18.4 Operations (6) Clearing the Timer The 16-bit up-count timer is cleared to 0000 in the following cases. • A reset • When counting starts after detection of a count start edge in pulse width count mode(6) (7) Details of Timer Mode Operation (a) Single-Shot Operation Mode When the timer is started in this mode, the timer counts up on each count clock.
18.4 Operations (e) Timer Period If the timer is started in single-shot mode after setting 0000 to PWCR, the timer overflows after 65536 counts and the count stops. The following formula calculates the time from the timer starting to the timer stopping.
18.4 Operations (g) Timer Operation Flowchart Count clock selection Operation and count mode selection Clear interrupt flag Settings Enable interrupt Set pulse output initial value Set value to PWCR Start by STRT bit Restart Reload operation mode Single-shot operation mode Reload PWCR value in timer Start count Start count...
18.4 Operations (8) Details of Pulse Width Count Mode Operation (a) Count Input Pins and Pin Selection The pins used to input the signal for pulse width counting are fixed as pin PWC0 for ch0, PWC1 for ch1, PWC2 for ch2, and PWC3 for ch3. Always set bits 4 and 5 of PWCSR to "00" on the MB90580. Table 18.4e Count Input Pin Selection (n = 3 to 0) PIS1 PIS0...
18.4 Operations (d) Count Mode and Count Operation The count mode can be selected from five different modes. The mode determines which part of the input pulse to measure. To accurately measure the width of high frequency pulses, a mode is available to divide the input pulses by a specified ratio and to measure the resulting period.
18.4 Operations (f) Pulse Width/Period Calculation Calculate the width or period of the measured pulse from the count result read from PWCR after the count ends as follows. … Measured pulse width or period (µs) n … Count result stored in PWCR ...
18.5 Precautions 18.5 Precautions (1) Changing Register Values Changing the values of the following PWCSR bits when the timer is operating is prohibited. Only change bit values before starting the timer or after operation stops. [bits 7, 6] CKS1, CKS0: Clock selection bits [bits 5, 4] PIS1, PIS0: Count input pin selection bits [bit 3] S/C: Count mode (single-shot or continuous) selection bit [bits 2, 1, 0] MOD2, MOD1, MOD0: Operating mode and count edge selection bits...
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18.5 Precautions (8) Divided Period Count Mode Note that the input pulses are divided when divided period count mode is used in pulse width count mode and therefore the pulse width calculated from the count result is an average value. (9) Restarting the Timer During Operation Depending on the timing, the following may occur when the timer is restarted after starting the count operation.
Chapter 19: Clock Monitor Function 19.1 Outline Clock Monitor Function is used to output the machine clock to a port pin. This clock output is generated by dividing the machineclock by 2 to 2 19.2 Block Diagram CKEN machine clock FRQ2 Clock division FRQ1...
Chapter 20: 16-Bit I/O Timer 20.1 Outline The 16-bit I/O timer consists of a 16-bit free-run timer, two output compare modules, and four input capture modules. The count values of this timer are used as the base timer for output compare and input capture. Using this function, two independent waveforms can be output based on 16-bit free-run timer to enable measurement of input pulse withs and external clock cycles.
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20.1 Outline Input capture (×4) The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of current counter value of the 16-bit free-run timer to the ICU data register (IPCP) upon an input of a trigger edge to the external pin.
20.3 Registers and Register Details 20.3 Registers and Register Details 20.3.1 16-bit free-run timer 16-bit Timer Data Register (Upper) Bit Number TCDTH Address: 00006D Read/write Initial value 16-bit Timer Data Register (Lower) Bit Number TCDTL Address: 00006C Read/write Initial value 16-bit Timer Control Status Register Bit Number Reserved...
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20.3 Registers and Register Details 20.3.1.1 16-bit free-run timer data register 16-bit Timer Data Register (Upper) Bit Number TCDTH Address: 00006D Read/write Initial value 16-bit Timer Data Register (Lower) Bit Number TCDTL Address: 00006C Read/write Initial value The data register can read the count value of the 16-bit free-run timer. The counter value is cleared to ’0000’...
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20.3 Registers and Register Details 20.3.1.2 16-bit free-run timer control status register 16-bit Timer Control Status Register Bit Number Reserved IVFE STOP MODE CLK1 CLK0 TCCS Address: 00006E Read/write Initial value [bit 7] Reserved bit Always write ’0’ to this bit. [bit 6] IVF This bit is an interrupt request flag of the 16-bit free-run timer.
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20.3 Registers and Register Details [bit 3] MODE The MODE bit is used to set the initialization condition of the 16-bit free-run timer. When ’0’ is set, the counter value can be initialized by a reset or a clear bit (bit 2: CLR). When ’1’...
20.3 Registers and Register Details 20.3.2 Output comparison The output compare module consists of 16-bit compare registers, compare output pins, and control regis- ter. If the value written to the compare register of this module matches the 16-bit free-run timer value, the output level of the pin can be reversed and an interrupt can be issued.
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20.3 Registers and Register Details 20.3.2.1 Compare register Output Compare Register 0, 1 Bit Number Address: 00005B OCCP0 (Upper) OCCP1 (Upper) 00005D Read/write Initial value Bit Number Address: 00005A OCCP0 (Lower) 00005C OCCP1 (Lower) Read/write Initial value This 16-bit compare register is compared with the 16-bit free-run timer. Since the initial register value is undefined, set a value before enabling the register.
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20.3 Registers and Register Details 20.3.2.2 Control status register Output Compare Control Status Register 0, 1 Bit Number Address: 00005F OCS1 CMOD OTE1 OTE0 OTD1 OTD0 Read/write Initial value Bit Number OCS0 Address: 00005E ICP1 ICP0 ICE1 ICE0 CST1 CST0 Read/write Initial value [bits 15, 14, and 13] Unused bits...
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20.3 Registers and Register Details [bits 7 and 6] ICP1 and ICP0 These bits are used as output compare interrupt flags. ’1’ is written to these bits when the compare reg- ister value matches the 16-bit free-run timer value. While the interrupt request bits (ICE1 and ICE0) are enabled, an output compare interrupt occurs when the ICP1 and ICP0 bits are set.
20.3 Registers and Register Details 20.3.3 Input capture This module detects a rising or falling edge or both edges of an externally input signal and stores the 16-bit free-run timer value in a register. In addition, this module can generate an interrupt upon detection of an edge.
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20.3 Registers and Register Details 20.3.3.1 Input capture data register Input Capture Data Register 0, 1, 2, 3 Address: 000061 Bit Number 000063 000065 IPCP0 (Upper) CP15 CP14 CP13 CP12 CP12 CP11 CP09 CP08 000067 IPCP1 (Upper) IPCP2 (Upper) Read/write IPCP3 (Upper) Initial value Address: 000060...
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20.3 Registers and Register Details 20.3.3.2 Control status register Input Capture Control Status Register ch0,1 & Ch2,3 Bit Number Address: 000068 ICS01 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 00006A ICS23 Read/write Initial value [bits 7 and 6] ICP1 and ICP0 These bits are used as input capture interrupt flags.
20.4 Operations 20.4 Operations 20.4.1 16-bit free-run timer The 16-bit free-run timer starts counting from counter value ’0000’ after the reset is released. The counter value is used as the reference time for the 16-bit output compare and 16-bit input capture operations. The counter value is cleared in the following conditions: •...
20.4 Operations 20.4.2 16-bit output compare In 16-bit output compare operation, an interrupt request flag can be set and the output level can be reversed when the specified compare register value matches the 16-bit free-run timer value. Sample output waveform when compare registers 0 and 1 are used (The initial output value is 0.) Counter value FFFF BFFF...
20.4 Operations 20.4.3 16-bit input capture In 16-bit input capture operation, an interrupt can be generated upon detection of a specified valid edge, fetching the 16-bit free-run timer value and writing it to the capture register. Sample input capture fetch timing Capture 0: Rising edge Capture 1: Falling edge Capture example: Both edges...
20.5 Timing 20.5 Timing 20.5.1 16-bit free-run timer count timing The 16-bit free-run timer is incremented based on the input clock (internal or external clock). When exter- nal clock is selected, the 16-bit free-run timer is incremented at the rising edge. Free-run timer count timing External clock input...
20.5 Timing 20.5.2 Output compare timing In output compare operation, a compare match signal is generated when the free-run timer value matches the specified compare register value. The output value can be reversed and an interrupt can be issued. The output reverse timing upon a compare match is synchronized with the counter count timing. Compare operation upon update of compare register When the compare register is updated, comparison with the counter value is not performed.
Chapter 21: ROM Correction Module 21.1 Outline When the setting of the address is the same as the ROM Correction Address register, the INT9 instruction will be executed. By processing the INT9 interrupt service routine, the ROM correction function can be achieved.
21.3 Registers and Register Details 21.3 Registers and Register Details Program Address Detect Register 0/1 byte byte byte access initial value undefined PADR0 1FF2H/1FF1H/1FF0H undefined PADR1 1FF5H/1FF4H/1FF3H Program Address Detect Control Status Register Bit number Address : 009E — — —...
21.3 Registers and Register Details 21.3.2 Program Address detect Control Status Register (PACSR) Program Address Detect Control Status Register Bit number Address : 009E — — — — — — AD1E AD0E PACSR Read/write (–) (–) (–) (–) (R/W) (–) (R/W) (–) Initial value...
21.4 Operations 21.4 Operations When the program counter indicates the same address as the ROM Correction Address register, the INT9 instruction will be executed. By processing the INT9 interrupt service routine, the ROM correction function can be achieved. There are two address registers, in each containing a compare enable bit. When the address register and the program counter are in agreement, and when the compare enable bit is at ‘...
21.5 Application Example 21.5 Application Example (1) System Structure EPROM F2MC16-LX pull up resistor connector (UART) Figure 21.5a System Structure Example (2) EPROM memory map address:content 0000H:number of bytes of the corrected program No. 0 (0 implies no ROM correction) 0001H:bit 7-0 program address No.
21.5 Application Example (6) INT9 interrupt In the interrupt routine, the address that produces the interrupt can be known by checking the stack program couter value. The information stacked during interrupt will be discarded. MB90580 FFFFFFh Erroneous Program External E PROM O Number of program byte Register setting...
21.5 Application Example Reset Read the 00h of E PROM INT9 0000h (E2PROM)=0 Read the Address 0001h~0003h (E2PROM) PADR0 (MCU) To Corrected Program JMP 000400h Read the Corrected Program 0010h~0090h (E2PROM) Corrected Program Execution 000400h~000480h 000400h~000480h (MCU) End of Corrected Program Enable compare JMP FF0050h MOV PACSR, #02h...
Chapter 22: ROM Mirroring Module 22.1 Outline In ROM Mirroring Module the FF bank of the ROM can be seen through the 00 bank when chosen during register setting. 22.2 Block Diagram ROM Mirrroring Register Address Area FF bank 00 bank Figure 22.2a Block Diagram of ROM Mirroring Module...
22.3 Registers and Register Details ADDRESS FFFFFF ROM Area ROM Area Address 1 010000 ROM Area 004000 002000 Address 2 RAM Area RAM Area 000100 0000C0 Internal IO Area IO Area Area 000000 When MI= ‘ 1’ When MI= ‘ 0’ Figure 22.3b Memory in Single Chip Mode ADDRESS FFFFFF...
Appendix A: I/O Map I/O Map Table A.1a lists the addresses assigned to the registers of each microcontroller resource Table A.1a I/O map Address Register Abbreviation Access Resource Initial value Port 0 data register PDR0 Port 0 XXXXXXXX Port 1 data register PDR1 Port 1 XXXXXXXX...
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A.1 I/O Map Table A.1a I/O map (Continued) Address Register Abbreviation Access Resource Initial value Clock division control register 0 CDCR0 Communication prescaler 0 0---1111 Reserved area Clock division control register 1 CDCR1 Communication prescaler 1 0---1111 Reserved area Interrupt /DTP enable register ENIR 00000000 Interrupt/DTP cause register...
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A.1 I/O Map Table A.1a I/O map (Continued) Address Register Abbreviation Access Resource Initial value XXXXXXXX Output Compare Register 0 OCCP0 XXXXXXXX XXXXXXXX Output Compare Output Compare Register 1 OCCP1 (Channel 0 To 1) XXXXXXXX Output Compare Control Status Register 0 OCS0 0000--00 Output Compare Control Status Register 1...
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A.1 I/O Map Table A.1a I/O map (Continued) Address Register Abbreviation Access Resource Initial value Serial mode register 4 SMR4 00000000 Serial control register 4 SCR4 00000100 UART4 Serial input register/serial output register 4 SIDR/ XXXXXXXX SODR4 Serial status register 4 SSR4 00001-00 Port 0 resistor register...
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A.1 I/O Map Table A.1a I/O map (Continued) Address Register Abbreviation Access Resource Initial value 1FF0 Program address detection register 0 XXXXXXXX 1FF1 Program address detection register 1 PADR0 XXXXXXXX 1FF02 Program address detection register 2 XXXXXXXX Program patch manipulation 1FF3 Program address detection register 3 XXXXXXXX...
APPENDIX B: Instructions B.1 Addressing In the F MC-16LX, the address format is determined by either the instruction’s effective address specification, or by the instruction code itself (implied addressing). B.1.1 Effective address field The address formats specified in the effective address field are shown in Table B.1.1a. Table B.1.1a Effective Address Field Code Notation...
B.1 Addressing B.1.2 Addressing Details (1) Immediate value (#imm) This format specifies the operand value directly. • #imm4 • #imm8 • #imm16 • #imm32 (2) Compressed direct address (dir) In this format, the operand specifies the low-order 8 bits of the memory address. Bits 8 to 15 of the address are specified by the DPR.
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B.1 Addressing (5) Register indirect (@RWj j = 0 to 3) This format accesses the memory address indicated by the contents of the general-purpose register RWj. When RW0/RW1 is used, bits 16 to 23 of the address are indicated by DTB; if RW3 is used, bits 16 to 23 of the address are indicated by SPB, and if RW2 is used, bits 16 to 23 of the address are indicated by ADB.
B.1 Addressing (10) Accumulator indirect (@A) This format has two types: one in which the contents of AL specify bits 00 to 15 of the address and DTB indicates bits 16 to 23; and one in which the low-order 24 bits of A specify bits 00 to 23 of the address. (11) I/O direct (io) In this format, the memory address of the operand is specified directly by the 8-bit displacement value.
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B.1 Addressing (17) Program counter relative branching address (rel) With this format, the address of the destination of a branching instruction is the sum of the value of the PC and the 8-bit displacement value. If the result exceeds 16 bits, the amount of the overflow is ignored and the bank register is not incremented or decremented;...
B.2 Instruction Set B.2 Instruction Set Table B.2a Explanation of Items in Table of Instructions Item Explanation Upper-case letters and symbols: ..Described as they appear in assembler. Mnemonic Lower-case letters: ......Replaced when described in assembler. Numbers after lower-case letters: ..Indicate the bit width within the instruction. Indicates the number of bytes.
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B.2 Instruction Set • Number of execution cycles The number of cycles required for the execution of an instruction is obtained by summing the value shown in the table for the “number of cycles” for the instruction in question, the compensation value (which depends on certain conditions), and the “number of cycles”...
B.2 Instruction Set Table B.2b Explanation of Symbols in Table of Instructions Symbol Explanation 32-bit accumulator The bit length varies according to the instruction. Byte:.... Low-order 8 bits of AL Word: ..16 bits of AL Long: ... 32 bits of AL:AH High-order 16 bits of A Low-order 16 bits of A Stack pointer (USP or SSP)
B.2 Instruction Set Table B.2c Effective Address Fields Number of bytes in Code Notation Address format address extension [Note] (RL0) Register direct (RL1) “ea” corresponds to byte, word, and long- – word types, starting from the left (RL2) (RL3) @RW0 @RW1 Register indirect @RW2...
B.2 Instruction Set Table B.2d Number of Execution Cycles for Each Form of Addressing Number of accesses for Number of execution Code Operand each form of addressing cycles for each form of addressing Listed in Table of Listed in Table of Instructions Instructions @RWj...
B.2 Instruction Set Table B.2f Compensation Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Byte boundary Word boundary Internal memory – External data bus (16 bits) – External data bus (8 bits) – Note: When the external data bus is used, it is necessary to add in the number of weighted cycles used for ready input and automatic ready.
B.3 Instruction Map B.3 Instruction Map Because the F MC-16LX operation codes each consist of one or two bytes, the instruction map consists of numerous pages. The structure of the instruction map is shown below. First byte Basic Page Map Bit manipulation Character string “ea”...
B.3 Instruction Map The correspondence between the actual instruction code and the instruction map is shown below. May not exist for some instructions Length differs according to the instruction Instruction code • • • First byte Second byte operand operand [Basic page map] [Extension page map] Note Note: Extended page maps are provided for bit manipulation instructions, character string manipulation...
Appendix C: The Flash Memory in the MB90F583 C.1 Outline There is a 1M-bit Flash memory (128K word x 8/64K word x 16) located at the FE~FF bank of the CPU memory map in MB90F583. With the flash memory interface circuit, it is possible for read access from and program access to the CPU.
C.2 Sector Structure of 1M Bit Flash Memory C.2 Sector Structure of 1M Bit Flash Memory Sector structure of 1M bit flash memory in MB90F583 is shown in Figure C.2a. The address in the Figure C.2a shows upper and lower address of each sector. When accessing from CPU, SA0 is set in the FE bank register and SA1~4 are set in the FF Bank register.
C.3 Flash Control Register (FMCS) C.3 Flash Control Register (FMCS) Flash control register (FMCS) is a register which is used during programming or erasing the flash memory. Flash Control Register (FMCS) Bit Number Address: 0000AE LPM1 INTE RDYINT Reserved Reserved LPM0 FMCS Read/write...
C.3 Flash Control Register (FMCS) [bit 4] RDY (ReaDY) This bit is used to indicate whether the flash memory is ready for programming/erasing. When this bit is set to “0”, programming or erasing the flash memory is not allowed. However, it is possible to issue read/reset command and sector erase suspend command when this bit is “0”.
C.4 Automatic Algorithm Initiation Method C.4 Automatic Algorithm Initiation Method To start the Automatic Algorithm in the flash memory, there are five types of commands, 2 types of read/reset, programming, chip erase and sector erase. For sector erase, there are the sector erase suspend and the sector erase resume command.
C.5 Execution Status of Automatic Algorithm In the flash memory, the programming or erasing can be done by Automatic Algorithm, so that there is a Hardware Sequence Flag in the flash memory, which indicates the operation status and the operation completion.
C.5 Execution Status of Automatic Algorithm C.5.1 Data polling flag (DQ7) Data polling flag is used to indicate whether the Automatic Algorithm is executing or completed by using data polling function. Table C.5.1a shows the status change of the data polling flag. •...
C.5 Execution Status of Automatic Algorithm C.5.2 Toggle bit flag (DQ6) Toggle bit flag is used to indicate whether the Automatic Algorithm is in progress or is completed by using toggle bit function. Table C.5.2a shows status change of the toggle bit flag. •...
C.5 Execution Status of Automatic Algorithm C.5.3 Exceeded timing limits flag (DQ5) Exceeded timing limits flag is used to indicate whether Automatic Algorithm has executed beyond the time (internal pulse count) specified in the flash memory. Table C.5.3a shows status change of the exceeded timing limits flag.
C.5 Execution Status of Automatic Algorithm C.5.4 Sector erase timer flag (DQ3) Sector erase timer flag is used to indicate whether the Automatic Algorithm is executed beyond the sector erase wait time after the sector erase command is issued. Table C.5.4a shows status change of the sector erase timer flag.
C.6 Details of Flash Memory Programming/Erasing C.6.2 Data Programming This section will describe how to issue the programming command to program the flash memory. To initiate Automatic Program Algorithm in the flash memory, the programming command found in command sequence table (refer to Section C.4, Automatic Algorithm Initiation Method, Table C.4a) can be used and it needs to be sent continuously to the target sector in the flash memory.
C.6 Details of Flash Memory Programming/Erasing C.6.3 Chip Erase This section will describe how to issue the chip erase command to erase the whole chip. To erase all data from the flash memory, the chip erase command found in command sequence table (refer to Section C.4, Automatic Algorithm Initiation Method, Table C.4a) can be used and needs to be send continuously to the target address in the flash memory.
C.6 Details of Flash Memory Programming/Erasing C.6.5 Suspend Sector Erase This section will describe how to issue the sector erase suspend command to suspend sector erase operation in the flash memory. During sector erase, it is possible to read data from the sector which is not being erased.
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Known bugs in HM MB90580 1. Chapter 20.4.5 Output Compare Unit ===================================== The documentation refers to outputs OUT0/1 and OUT2/3. There does not exist OUT2 and OUT3 (see pinning). So compare register 0 corresponds to OUT0 only and compare register 1 to OUT1. last updated : 05-03-98...