Fujitsu F2MC-16LX MB90580 Series Hardware Manual page 232

15.3 Registers and Register Details
[Bit 4] RELD (Reload)
This bit enables reload operations. When RELD is "1", the timer operates in reload mode. In this mode,
the timer loads the reload register contents into the counter and continues counting whenever an
underflow occurs (when the counter value changes from 0000
operates in one-shot mode. In this mode, the count operation stops when an underflow occurs due to
the counter value changing from 0000
OUTE
0
1
1
1
1
[Bit 3] INTE (Interrupt enable)
Timer interrupt request enable bit. When INTE is "1", an interrupt request is generated when the UF bit
changes to "1". When INTE is "0", no interrupt request is generated, even when the UF bit changes to
"1".
[Bit 2] UF (Underflow)
Timer interrupt request flag. UF is set to "1" when an underflow occurs (when the counter value
changes from 0000
bit has no meaning. Read as "1" by read-modify-write instructions.
[Bit 1] CNTE (Count enable)
Timer count enable bit. Writing "1" to CNTE sets the timer to wait for a trigger. Writing "0" stops count
operation.
[Bit 0] TRG (Trigger)
Software trigger bit. Writing "1" to TRG applies a software trigger, causing the timer to load the reload
register contents to the counter and start counting. Writing "0" has no meaning. Reading always returns
"0". Applying a trigger using this register is only valid when CNTE = "1". Writing "1" has no effect if
CNTE = "0".
212 Chapter 15: 16-Bit Reload Timer (with Event Count Function)
RELD OUTL
X X General-purpose port
0 0
Output an "H" level square waveform during counting.
0 1 Output an "L" level square waveform during counting.
1 0 Toggle output. "L" level at count start.
1 1 Toggle output. "H" level at count start.
to FFFF ). Cleared by writing "0" or by the intelligent I/O service. Writing "1" to this
H H
to FFFF ..
H H
Output Waveform
to FFFF ). When RELD is "0", the timer
H H
MB90580 Series