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A.1 Instruction Set Summary
Table A-1
is a quick reference to the CPU12 instruction set. The table shows source
form, describes the operation performed, lists the addressing modes used, gives ma-
chine encoding in hexadecimal form, and describes the effect of execution on the con-
dition code bits.
A.2 Opcode Map
Table A-2
displays the mnemonic, opcode, addressing mode, and cycle count for
each instruction. The first table represents those opcodes with no prebyte. The second
page of the table represents those opcodes with a prebyte value of $18. Notice the first
hexadecimal digit of the opcode (shown in the upper left corner of each cell) corre-
sponds to column location, while the second hexadecimal digit of the opcode corre-
sponds to row location.
A.3 Indexed Addressing Postbyte Encoding
Table A-5
shows postbyte encoding for indexed addressing modes. The mnemonic
for the indexed addressing mode postbyte is xb. This is also the notation used in in-
struction glossary entries.
decimal format. The first digit of the postbyte is represented by the value of the
columns in the table. The second digit of the postbyte is represented by the value of
the row.
A.4 Transfer and Exchange Postbyte Encoding
Table A-4
shows postbyte encoding for transfer and exchange instructions. The mne-
monic for the transfer and exchange postbyte is eb. This is also the notation used in
instruction glossary entries. The first digit of the instruction postbyte is related to the
columns of the table. The second digit of the postbyte is related to the rows. The body
of the table shows actions caused by the postbyte.
A.5 Loop Primitive Postbyte Encoding
Table A-6
shows postbyte encoding for loop primitive instructions. The mnemonic for
the loop primitive postbyte is lb. This is also the notation used in instruction glossary
entries. The loop primitive instructions are DBEQ, DBNE, IBEQ, IBNE, TBEQ, and
TBNE. The first digit of the instruction postbyte corresponds to the columns of the ta-
ble. The second digit of the postbyte corresponds to the rows. The body of the table
shows actions caused by the postbyte.
CPU12
REFERENCE MANUAL
APPENDIX A
INSTRUCTION REFERENCE
Table A-3
presents the same information in two-digit hexa-
INSTRUCTION REFERENCE
MOTOROLA
A-1
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