Sony CXD2701Q Data Book page 115

SONY,
CXD11S0AP/AQ
No,
Symbol
I/O-
Description
17-20
N.C
21
MCK2
I
Master
clock
input 2.
Master clock
ACK
inside the IC
has
the
same
frequency.
To
input
the master clock through
MCK2
fix
MCK1
to
+5V
or
to
GND.
22-26
N.C
27
SI
1
Input pin
for
1
sampling 2ch
serial
data.
Data
format
complement
on
two.
At
last
LSB
various
modes
32/24/16
bit
available.
28
SO
1
sampling 2 channel
serial
data output
pin.
Data
format
complement on
two.
At
last
LSB,
various
modes
32/24/1
6bit
available.
29
BCK
!
Serial bit
clock
input pin of
serial
input
data
SI
and
serial
output data
SO.
With the
rising
edge
of this
BCK
serial input data
is
taken
In
and
with the
falling
edge
serial
output data
is
sent
out.
30
LRCK
1
Serial I/O
sampling frequency clock
input pin.
Transfers chl data
when
level
at
'H*
and ch 2 data
when
level at 'L\
31
XOVF
O
Adder-subtracter overflow detection output.
Outputs
V
during overflow
detection.
32-33
N.C
34
A6
O
External
DRAM
address
output
A6
35
A3
o
External
DRAM
address
output
A3
36
A4
External
DRAM
address
output
A4
37
AS
External
DRAM
address
output
A5
38
A7
o
External
DRAM
address
output
A7
39-43
N.C
44
XCLR
II
Test
pin.
Normally
fixed to
5V.
45-48
N.C
49
Vcc
-
+5V
supply
pin
50-55
i
N.C
56 A1 Extern
af
DRAM
address
output
A1
57-60
N.C
61
A2
o
External
DRAM
address
output
A2
62-66 N.C
67 A0
External
DRAM
address output
A0
68
XRAS
o
External
DRAM
low address
strobe output pin.
69
XWSO
When DYSL
is
at
'L\
turns
to
serial
data output
pin,
and
operates according
to
the various
serial I/O
modes.
When DYSL
is
at
H
!
turns
into
the
write
enable
output
pin of the external
DRAM.
70
DIO
I/O
Turns
to serial
data input pin
when
DYSL
is
at
'L'
and
takes
in
according
to
the various
serial I/O
modes.
Turns
into external
DRAM
data I/O pin
when
DYSL
is
at "H*
to
assume
a
common
bus with
DRAM
data
input Din
and data output Dout.
71
XCAS
External
DRAM
column addess strobe output
pin.
72-73
N.C
I
m