Sony CXD2701Q Data Book page 113

SONY,
CXD1160AP.AQ
Pin Configuration
and
Descripion
(CXD1160AP)
Pin Configuration
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Pin Description
No.
Symbol
I/O
Description
1
SDT
I
Serial
data input pin that
receives
commands,
coefficient
and
I/O control
transfer
from
the
microcomputer.
In
each
transfer
modes,
single 40-bit
block
is
transferred
at
a
time.
2
SCK
I
SDT
serial
clock
input pin.
Takes
in
data
with the
rising
edge.
3
XSLD
I
Latch
input pin that
serves
to
latch
inside the iC
1
block
of serial
data 40bit
in
length active
at
t,'.
4
SI02
I
Input pin.
Sets the
number
of
BCK
clocks used
for
data transfer
per channel
(ch1
and
2) in
one
sampling
section.
When
fixed to
GND
it
turns to 32bit
clock
mode.
When
fixed to
+5V
it
turns
to
24bit clock
mode.
5
DYSL
I
Delay
I/O
mode
select input pin.
When
GND
is
fixed
it
turns
to
serial
mode.
Operates
similarly
as
serial
I/O.
Fixed
at
+5V
it
turns to delay
mode.
Connected
to
an
external
DRAM
(64Kbit)
composes
a delay
line
for
2
channels.
6
TST
I
Test
pin.
Normally
fixied to
GND.
7
Vss
GND
pin.
8
MCK1
i
Master
clock input
1.
Master
clock
ACK
inside the IC
is
half this
frequency.
To
input
the master clock through
MCK1
fix
MCK
2 to
+5V.
9
MCK2
I
Master clock
input 2.
Master clock
ACK
inside the IC
has the
same
frequency.
To
input
the
master clock
through
MCK2
fix
MCK1
to
+5V
or
to
GND.
10
SI
I
Input pin
for
1
sampling 2ch
serial data.
Data
format
complement on
two.
At
last
LSB, various
modes
32/24/1
6bit
available.
11
SO
1
sampling 2 channel
serial
data output
pin.
Data format
complement on
two.
At
last
LSB,
various
modes
32/24/1 6bit available.
12
BCK
I
Serial
bit
clock
input pin of
serial
input
data
SI
and
serial
output
data SO.
With the
rising
edge
of
this
BCK
serial input
data
is
taken
in
and
with the
falling
edge
serial
output data
is
sent
out.
13
LRCK
I
Serial I/O
sampling frequency clock
input
pin.
Transfers chl data
when
level
at
'H'
and ch 2 data
when
level at
'L'.
14
XOVF
Adder-
subtracter
overflow detection
output,
Outputs
'L'
during overflow
detection.
15
A6
External
DRAM
address
output
A6
16
A3
External
DRAM
address output
A3
17
A4
O
External
DRAM
address
output
A4
18
A5
External
DRAM
address
output
A5
I
109