Uart Input Port Change Registers (Uipcrn) - Motorola DigitalDNA ColdFire MCF5272 User Manual

Register Descriptions
7
Field
Reset
R/W
Address
Figure 16-8. UART Transmitter Buffers (UTBn)

16.3.8 UART Input Port Change Registers (UIPCRn)

The input port change registers (UIPCRn), Figure 16-9, hold the current state and the
change-of-state for CTS.
7
Field
Reset
R/W
Address
Figure 16-9. UART Input Port Change Registers (UIPCRn)
Table 16-7 describes UIPCRn fields.
Bits Name
7–5 — Reserved, should be cleared.
4 COS Change of state (high-to-low or low-to-high transition).
0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS].
1 A change-of-state longer than 25–50 µs occurred on the CTS input. UACRn can be programmed to
generate an interrupt to the CPU when a change of state is detected.
3–1 — Reserved, should be cleared.
0 CTS Current state. Starting two serial clock periods after reset, CTS reflects the state of CTS. If CTS is
detected asserted at that time, COS is set, which initiates an interrupt if UACRn[IEC] is enabled.
0 The current state of the CTS input is asserted.
1 The current state of the CTS input is negated.
16.3.9 UART Auxiliary Control Registers (UACRn)
The UART auxiliary control registers (UACRn), Figure 16-7, control the input enable as
well as the RTS control based on the receiver FIFO level.
16-12
MBAR + 0x10C,0x14C
5
— COS
0000_011
MBAR + 0x110 (UIPCR0), 0x150 (UIPCR1)
Table 16-7. UIPCRn Field Descriptions
MCF5272 User's Manual
TB
0000_0000
Write only
4 3
111
Read only
Description
0
1 0
CTS
CTS