Programmable Interrupt Wakeup Register (Piwr) - Motorola DigitalDNA ColdFire MCF5272 User Manual

Interrupt Controller Registers
31 30 29
Field INT1 INT2 INT3 INT4
Reset
15
Field
Reset
R/W
Addr
Figure 7-7. Programmable Interrupt Transition Register (PITR)
Table 7-5 describes PITR fields.
Bits Name
31–28, — 0 Triggering edge of external interrupt input is low-to-high (positive edge triggered).
1 Triggering edge of external interrupt input is high-to-low (negative edge triggered).
6, 5
27–7, — Reserved, should be cleared.
4–0

7.2.5 Programmable Interrupt Wakeup Register (PIWR)

The programmable interrupt wakeup register (PIWR), Figure 7-8, is used to specify which
interrupt sources are capable of causing the CPU to wake up from low-power SLEEP or
STOP modes when their source is active. All sources are disabled on reset. Note that only
the external interrupt pins INT[6:1] can wake up the CPU from STOP mode.
If more than one interrupt source has the same interrupt priority level (IPL) programmed in
the ICRs, the interrupt controller daisy chains the interrupts with the priority order
following the bit placement in the PIWR, with INT1 having the highest priority and SWTO
having the lowest priority as shown in Figure 7-8.
7-8
28 27
0000_0000_0000_0000
—
0000_0000_0000_0000
MBAR + 0x034
Table 7-5. PITR Field Descriptions
MCF5272 User's Manual
—
7 6 5 4
INT5 INT6
R/W
Description
16
0
—