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7 DETAILS OF INSTRUCTIONS
cv.al %rd, %rs
Function
Data conversion from 32 bits to 24 bits
Standard)
Extension 1) Unusable
Extension 2) Unusable
15 14 13 12 11 10
Code
0
0
1
|
|
IL
IE
C
Flag
|
|
–
–
–
Mode
Src: Register direct %rs = %r0 to %r7
Dst: Register direct %rd = %r0 to %r7
CLK
One cycle
Description
(1) Standard
The eight low-order bits of the rs register are transferred to the eight high-order bits of the rd
register.
(2) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after a
branch instruction with the "d" bit.
Example
When the R1 register contains 0xff and the R0 register contains 0x0
cv.al
7-28
rd(23:16) ← rs(7:0), rd(15:0) ← rd(15:0)
9
8
7
|
|
0
1
0
r d
|
|
|
|
|
V
Z
N
|
|
|
–
–
–
23
rs
X
23
16 15
rd
8 bits
%r0,%r1
; r0 = 0xff0000
Seiko Epson Corporation
6
5
4
3
2
1
0
|
1
1
1
1
r s
|
|
|
|
|
8 7
15
Unchanged
0
8 bits
0
0
S1C17 CORE MANUAL
(REV. 1.2)
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