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1.4.10 Code compatibility
The V
4110 core is designed in consideration of the program compatibility to other V
R
However since it has some differences from other processors on their architecture, it cannot necessarily execute all
programs that can be executed in other V
necessarily execute all programs that can be executed in the V
Matters that should be paid attention to when porting programs between the V
processors are listed below.
• A 16-bit length MIPS16 instruction set is added in the V
• Multiply-add instructions (MADD16, DMADD16) are added in the V
• Instructions for power modes (HIBERNATE, STANDBY, SUSPEND) are added in the V
power modes.
• The V
4110 core does not support floating-point instructions since it has no Floating-Point Unit (FPU).
R
• The V
4110 core does not have the LL bit to perform synchronization of multiprocessing. Therefore, it does not
R
support instructions that manipulate the LL bit (LL, LLD, SC, SCD).
• The CP0 hazards of the V
For more information about each instruction, refer to V
manuals of each product other than the V
Instructions supported by each of the V
Table 1-7. List of Instructions Supported by V
Products
Supported instructions
MIPS I
MIPS II
MIPS III
LL bit
manipulation
MIPS IV
MIPS16
Multiply-add
Floating-point operation
Power mode transition
46
CHAPTER 1 INTRODUCTION
-Series processors, and also other V
R
4110 core are equally or less stringent than those of the V
R
4100 Series.
R
Series processors are listed below.
R
V
4181
V
4121
R
R
TM
V
4111
V
4122
R
R
A
A
A
A
A
A
N/A
N/A
N/A
N/A
A
A
A
A
(16 bits)
(32 bits)
N/A
N/A
A
A
User's Manual U14272EJ3V0UM
4110 core.
R
4110 core and other V
R
4110 core.
R
4110 core.
R
4100 Series Architecture User's Manual, and user's
R
Series Processors
R
TM
TM
V
4300
V
5000A
R
R
TM
V
4305
R
TM
V
4310
R
A
A
A
A
A
A
A
A
N/A
A
N/A
N/A
N/A
N/A
A
A
N/A
A
-Series processors.
R
-Series processors cannot
R
-Series
R
4110 core to support
R
4000.
R
TM
TM
V
5432
V
10000
R
R
TM
V
12000
R
A
A
A
A
A
A
A
A
A
A
N/A
N/A
A
N/A
(32 bits)
A
A
A
N/A
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