Page 1 Hardware Z-100 Series Computers • • ' 593-0038-04 CONSISTS OF MANUAL 595-2918-04 FLYSHEET MAIN BOARD SCHEMATIC 597-2792-04 585%018-02 TAB SET (VOL. I) VIDEO LOGIC SCHEMATIC 597-3437 585-0019-01 TAB SET (VOL. II) VIDEO DEFLECTION SCHEMATIC 5974438 585-002041 SCHEMATIC ENVELOPES FLOPPY CONTROLLER SCHEMATIC...
Page 2 This Document was scanned and contributed by:...
Page 3 About These Manuals This technical manual set for the H/Z-100 Series of Desktop Computers (Low-Profile and All-in-One) is divided into a number of volumes for easy handling and quick reference. • Ha r dware Volumes 1 and 2 — These two volumes contain...
Page 4: Table Of Contents
CONTENTS General Information Chapter 1 Introduction . System Description Disassembly Chapter 2 Main Board Description User Options and Jumpers Programming Information 2.19 Theory of Operation Circuit Description 2 23 Parts List . 2 92 Semiconductor Identification Circuit Board X-Ray View 2.136 Interconnect Pin Definitions 2.137...
Page 5 CONTENTS Chapter 5 Video Deflection Board Circuit Description . Troubleshooting Recalibration Parts List . 5.8 Circuit Board X-Ray View . 5.11 Floppy Disk Controller Chapter 6 Description .. User Options . . . 63 Programming Data 6.21 Theory of Operation 6.23 Circuit Description .
Page 6 CONTENTS Programming Data Chapter 10 Description 10.2 General Information .. 10.3 Devices Permitting User Programming 10.10 Port Addresses 10.11 Z-DOS Initialization Sequence . . 10.14 ASCII Chart . . 10.30 Escape Codes 10.38 10.42 Definitions Key Code Chart 10.52 Keypad Code Chart 10.59 Function Key Code Chart ..
Page 8: Chapter 1 General Information
Page 1.1 Chapter 1 GENERAL INFORMATION Introduction The Z-100 Series Desktop Computers (Low-Profile and All-in- One Models) are a series of profession computers that easily handle demanding computer tasks. Advanced state-of-the-art digital electronics and unique engineering concepts have been combined to form a truly exceptional and versatile family of computers.
Page 9: System Description
Page 1.2 GENERAL INFORMATION System Description The Z-100 Series All-in-One and Low-Profile Computers pro- vides expandability; 8088, 8086, and 8080 code compatibility; and a 5MHz clock for computing power. Expandability is provided through a 5-slot backplane on the main board. This allows you to expand your system with Heath/Zenith Data Systems peripherals and options or IEEE 696 standard S-100 cards from outside suppliers.
Page 10 page 1.3 GENERAL INFORMATION System Description System Modules Refer to Pictorial 1-1 for the following discussion. Power Supply The power supply is an on line, switching power supply, pro- viding +12VDC, — 12VDC, +5VDC, and — 5VDC. It is cooled by an internal fan and is protected from overvoltage, under- voltage, overcurrent, and overtemperature operation.
Page 11: Circuit
page 1.4 GENERAL INFORMATION System Description Main Board The main circuit board contains the two processors, an 8085 and an 8088, (CPU's — referred to as the master processors); the 5-slot backplane with an S-100 IEEE 696 bus; capacity for 3 banks of 64K devices for user memory, up to 192K; 8041A keyboard processor and connections for the keyboard;...
Page 12 Note: Standard Z-DOS, CP/M-85, and CP/M-86 operating systems, as supported by Zenith Data Systems, are configured to support only two of each drive size. If additional drives are required, the operating systems will have to be modified by the user.
Page 13 Winchester drive at this time for single user installations. Other Options Other optional S-100 cards are available from Zenith Data Systems. They include the NET-100 Z-LAN™ network card and interface software, the Z-204 multiport input/output card (available with or without ring detect), and the Z-205 memory card (with a capacity for 256K additional RAM memory).
Page 14: Disassembly
Disassembly There are a number of versions of both the Low-Profile and All-in-One Z-100 Series available. The variations in the config- urations are limited to 5.25-inch drive size (both full-sized and half-height versions are available) and whether or not the op- tional Winchester disk system is installed in the computer.
Page 15 page 1.8 GENERAL INFORMATION Disassembly Refer to Pictorial 1-2 and move the metal slides to the rear approximately 1/4-inch as shown. Carefully lift off the cabinet top and set it to one side. (On the All-in-One models, you will have to use a flat-bladed screwdriver as illustrated in the pictorial.
Page 16: Card Removal
Page 1.9 GENERAL INFORMATION Disassembly Card Removal Refer to Pictorial 1-3. The various cards in your computer can be removed as your needs dictate. However, be aware that you will occasionally have to remove cables from several different cards to remove one card. For instance, if you want to remove the floppy disk controller card and you have a Winchester card installed to the back ofit (as viewed from the front of the computer, you will have...
Page 17 page 1.10 GENERAL INFORMATION Disassembly Display and Disk Drive Assembly (All-in-One Computer) Refer to Pictorial 1-4. Remove screw A a n d c o mpletely loosen the four B screws (these last four may be accessed through holes in the cabinet slides. Lift the display and disk drive as- sembly up and forward a short distance.
Page 18 page 1.11 GENERAL INFORMATION Disassembly Floppy Disk Systems only; refer to Pictorial 1-5 and re- move: the flat cable from the floppy disk controller card, the power supply cable(s) at the drive(s), and the video signal/power cable on the video deflection board.
Page 19 page 1.12 GENERAL INFORMATION Disassembly Winchester Disk Systems only; refer to Pictorial 1-6 and remove: the two flat cables (134-1279 and 134-1281) from the Winchester controller card, the flat cable (134-1144) from the floppy disk con- troller card, the power cable from the Winchester controller card, the power supply cables from the drives, and the video signal/power cable on the video deflection board.
Page 20 GENERAL INFORMATION pisassembly Low-Profile Front Panel and Dis isk Drive Assembly Refer to Pictorial 1-7. Remove the four screws a rews at A and two locking pins at L ift the front panel and disk drive assembly out o of the computer an o d t the front a short distance.
Page 21 page 1.14 GENERAL INFORMATION Disassembly Refer to Pictorial 1-8 Floppy Disk Systems only; remove the f lat cable from the floppy disk drives and • the p o wer supply cable(s) at the drive(s). DR IVE Set the assembly aside. s U BAs s EM BLv::;.::::::: : : .
Page 22 page 1.15 GENERAL INFORMATION Disassembly Refer to Pictorial 1-9. Winchester Disk Systems only; remove: the two flat cables (134-1279 and 134-1281) from the Winchester controller card, the power cable from the Winchester controller card, the flat cable (134-1284) from the floppy disk con- troller card, and the power supply cables at the drives.
Page 23 page 1.16 GENERAL INFORMATION Disassembly Keyboard Refer to Pictorial 1-10. Remove the two screws at A from near the top of the keyboard. Low-Profile models only; remove the two locking pins at B from near the rear of the computer. Lift off the keyboard shell.
Page 24 Page 1.17 GENERAL INFORMATION Disassembly Refer to Pictorial 1-11. Move the keyboard forward and unplug the two cables from the main board. Set the keyboard to one side. NIA IN KEYSOARD Pictorial 1-11. Removing the Keyboard...
Page 25 page 1.18 GENERAL INFORMATION Disassembly Power Supply Refer to Pictorial 1-12. NOTE: Your power supply may look different than the one illustrated. Unplug remaining power cables. Remove the four screws at A from the rear panel as illustrated. Remove the two screws at B from the front bottom of the power supply that hold it to the base.
Page 26 Page 1.19 GENERAL INFORMATION Disassembly Remove all cards from the card cage and set them to one side. Remove the two screws at C from the rear panel as illus- trated. Remove the four screws at D from the base as illustrated. Remove and set the card cage to one si de.
Page 27 page 1.20 GENERAL INFORMATION Disassembly Video Logic Circuit Board Refer to Pictorial 1-13. Remove the three screws holding the board to the three hex mounting spacers. Unplug the two cables from the main board. Remove the circuit board and set it to one side. 3 0 0 3 0 gO gQ >~~ o~...
Page 28 page 1.21 GENERAL INFORMATION Disassembly Main Board Refer to Pictorial 1-14. Remove the three hex mounting spacers at A from the main board. Remove the nine screws at B from the main board. Remove the main board and set it to one side. This completes the disassembly of the modules of your com- puter.
Page 29 page 1.22 GENERAL INFORMATION Disassembly Disk Drive Modules There are several different configurations of disk drives for your computer. These include units with one or two floppy disk drives, one floppy disk drive and one Winchester drive, and similar modules with half-height floppy disk drives. All-in-One Models Refer to Pictorial 1-15.
Page 30 page 1.23 GENERAL INFORMATION Disassembly DR IVE ASSEMBLY CHASSIS (7(iii lTtlTt Tt TllTrl D l( i c 6-32 x 3/8" (r~::: HEX HEAD I II I SCREW I II I II I II GROUND I ll STRAP I I l 1 l' I I( I I (...
Page 31 Page 1.24 GENERAL INFORMATION Disassembly Refer to Pictorial 1-16. This pictorial illustrates a Winchester and full-sized floppy disk system. Your system, whether it is a half-height or floppy disk only version will be similar. Remove the three screws at A and remove the front panel and panel from the assembly.
Page 32 Page 1.25 G ENERAL INFORMATION Disassembly Winchester Systems Refer to Pictorial 1-17. Remove the data separator cable assembly 134-1380 from the data separator board. Remove the four screws at A a n d r emove the data separator board; set it to one side. Full-sized floppy disk drives only;...
Page 33 page f.26 GENERAL INFORMATION Disassembly Refer to Pictorial 1-18. Half-height floppy disk drives only; remove the four screws at B and remove the floppy disk drive. Half-height floppy disk drives only; remove the four screws at C and remove the Winchester disk drive. DR (VE DRIVE 0 CHASSIS...
Page 34 Page 1 27 GENERAL INFORMATION Disassembly Low-Profile Models Get the front panel and disk drive assembly that you set to one side earlier. Carefully remove the front panel from the front of the assem y . mbl . Set it to one side where the tacky side will notbecontaminatedbydust, lint, paper, orot ero j her ob'ects.
Page 35 This completes the disassembly section of your manual. Parts are identified in the various parts lists through this and other technical manuals published by Zenith Data Systems. A com- plete service manual is also available from Heath replacement parts or your local dealer.
Page 36 Page 1.29 GENERAL INFORMATION Disassembly DISK DRIVE — L. ! i~ DRIVE SHELF L EFT S I D E B RAC K E T 6 — 32 X3/ 8 H EX H E A D SCREW DR IV E S HIEL D el' p~ ~ R IGHT S I D E B RACK E T...
Page 38: Programming
Page 2.f Main Board Description User Options and Jumpers Programming Information Theory of Operation Circuit Description .. 2 23 Replacement Parts List . 2.92 Semiconductor Identification Circuit Board X-Ray Views 2.136 Interconnect Pin Definitions 2.137 Schematic . (Inside Envelope at rear of manual.)
Page 39: Description
page 2.2 DESCRIPTION The main board is the permanent bus master unit in the S-100 bus system and contains two microprocessors, an 8085 and an 8088. Both operate at 5 MHz. The 8088 has a 16-bit inter- nal architecture that interfaces to an 8-bit external architec- ture, while the 8085 is a pure 8-bit processor.
Page 40 OIjljc 2' 2 J104 2 • J105 ,.'ll J106 2" (ON SOME- 2222 BOARDS) J109g rcn J111 s Pictorial 2-1 Main Circuit Board...
Page 41: User Options And Jumpers
Page 2.3 USER OPTIONS AND JUMPERS Refer to Pictorial 2-1 as you read the following information. Switch S101 DIP switch S101 selects the following functions during power- up or master reset. Set the switches for your system and pre- ferences. Switch S101, Section Descri tion...
Page 42 Page 2.4 USER OPTIONS AND JUMPERS Circuit Board Jumpers The main board circuit board jumpers perform the following functions: J101 — Selects whether +5VDC or address line BA14 is applied to pin 27 of the PROM. The position shown has + 5VDC connected to pin 27 for an 8K x 8 o r 1 6 K x 8 PROM.
Page 43 page 2.5 USER OPTIONS AND JUMPERS J108 — No jumper is presently used at this position. If a jumper plug is installed, serial port B will generate an interrupt when the transmitter is empty (TXEMT active) in addition to its normal interrupts. J109 —...
Page 44: Programming Information
Page 2.6 PROGRA M M ING INFORMATION The information in this section concerns the main board only and is meant to be used by the experienced programmer. Programming for the entire system is contained in "Pro- gramming Data" toward the end of this manual. Port Addresses The following port addresses are for devices located on the main board.
Page 45 page 2.7 PROGRA M M ING INFORMATION Oevice Name Port Address HEX 2661 Senal A — 2661 Serial A — 2661 Serial A — 2661 Serial A 8253 Timer — 8253 Timer — 8253 Timer — 8253 Timer 68A21 Parallel —...
Page 46 Page 2.8 PROGRA M M ING INFORMATION Dip Switch Port (FF) The function of the DIP switch bits are defined by the monitor program in ROM on power-up or master reset, but they may be redefined and reread by the operating system when it is loaded.
Page 47 Page 2.9 PROGRA M M ING INFORMATION Processor Swap Port (FE) Processor swap is accomplished by the presently selected processor writing to bit 7 of the processor swap port (PSP). If a 1 is written, the 8088 is selected. A 0 selects the 8085. (See the following chart.) When the processor swap occurs, the newly selected proces- sor can be restarted where it left off, or, an interrupt (l1 on...
Page 48 Page 2.10 PROGRA M M ING INFORMATION High Address Latch (FD) The 8085 in its natural state has 16 bits of addressing capabil- ity. By writing to the high address latch, HIGHADDR, the user can control the upper eight address bits placed onto the bus, and thereby generate 24-bit addresses.
Page 49 Page 2.11 PROGRA M M ING INFORMATION Memory Control Latch Port (FC) This port controls the configuration of memory, both ROM and RAM. It also provides an option for checking RAM parity. The options, which affect how the ROM is addressed, are enabled by writing to the memory control latch (MEMCTL) port.
Page 50 Page 2.12 PROGRA M M ING INFORMATION The following chart shows which port bits control the four ROM configurations. BITS DEF I N ITION Option 0 01 = Option1 3 , 2 10 = Option 2 11 = Option 3 Option 0, the power-up or master reset configuration, makes the code in ROM appear to be in all of memory when reads are performed.
Page 51 Page 2.13 PROGRA M M ING INFORMATION 8253 Timer Status Port (FB) Port A ddress Timers Timer 1 The timer circuitry consists of an 8253 timer IC and several other IC's. (See the Timer Port Address Block Diagram.) The 8253 has three channels. Each channel has a input clock ( —...
Page 52 Page 2.14 PROGRA M M ING INFORMATION DE F I NITION = Use 16-bit binary counter Use 4-decade binary coded decimal counter 000 = Mode0 Mode1 = Mode 3 X 10 = Mo d e 2 100 = Mode4 Mode5 0 0 = Counter latch Read/load least...
Page 53 Page 2.15 PROGRA M M ING INFORMATION 250 KHz I4psI CLK 0 8253 CH 0 T IMER OUT 0 8253 T IMER CLK 1 CH I DATA LATCH CLK 2 OUT 2 CH 2 I NT. 8259A Interrupts (FO-F3) The following list shows the possible interrupts. The slave 8259A handles only the vector interrupts you configure your hardware to generate.
Page 54 Page 2.16 PROGRA M M ING INFORMATION 68A21 Parallel Port (EO-E3) Port Address Peripheral EO(CRA2 = 1 CLPHT LPSWT CVINT VIDINT INIT STROBE Register A Data EO(CRA2 = 0 Direction Register A Control IRQA1 IRQA2 CA2 Control CRA2 CA1 Control Register A E2(CRB2 = 1 ERROR...
Page 55 Page 2.17 PROGRA M M ING INFORMATION This printer port uses portions of both port A and port B in the 68A21. The eight bits of data out to the printer, PD1 — PD8, are assigned to port A, bits 0 to 1, and to port B, bits 2 through 7 assigned to port A, bits 0 to 1, and to port B, bits 2 through 7 respectively.
Page 56 Page 2.18 THEORY OF OPERATION The Z-100 main board has five major parts: the CPU, the memory, the interrupt circuitry, the keyboard and timer, and the l/0 circuitry. Each of these parts is shown in the block diagrams in Pictorials 2-1 through 2-5. The CPU As you can see in Pictorial 2-2, the CPU can be one of two different processors, either an 8085 or an 8088.
Page 57 page 2.19 THEORY OF OPERATION NM I OR/ POWER EA IL OPT ION ADDRESS TRAP 8-BIT CPU 8088 SELECT HOLD 8085 (5MHz) INTR 8085 16- 8 IT C PU SELECT DMA REQ 8088 (5MHz) INTR DATA ADDRESS AO-15 SELECTION LOG IC 4 BIT LATCH (1/2 U624)
Page 58: Theory Of Operation
Page 2.20 THEORY OF OPERATION Memory Pictorial 2-3 shows that the memory portion of the main board consists of memory selection circuitry, parity computation and storage, an address multiplexer, a refresh circuit, up to 192K of data and parity RAM, and up to 32K of ROM. The selection circuitry decodes the address bits from the CPU to access the proper memory or port locations.
Page 59: Theory Of Operation
Page 2.21 THEORY OF OPERATION The address multiplexer converts the 16-bit address bus to the 8-bit row and column addresses required by the RAM chips. The refresh circuit prevents the data in RAM from decaying. The data and parity RAM is made up of 64K increments, while the ROM consists of a single EPROM or ROM chip.
Page 60 page 2 22 THEORY OF OPERATION Keyboard As shown in Pictorial 2-5, this circuitry is made up of a keyboard and a keyboard encoder. The encoder detects a closed key contact in the keyboard and converts it into the corresponding ASCII code for that key.
Page 61: Circuit Description 2
8-bit processor. Because the 8085 uses the same instruction set as the Intel 8080, the Z-100 computer can maintain a high degree of software compatibility with previous Zenith Data Systems Computers. To understand the 8085, study the pin-out and basic timing discussion that follows.
Page 62 Page 2.24 CIRGUIT DESGRIPTION ALE, pin 30 (address latch enable). This output line pulses high, and then low, when either the memory or I/O address is on lines AO-A7. The external circuits use the negative-going transition to latch the address information. The falling edge of ALE is also used to strobe CPU status information.
Page 63 Page 2.25 CIRCUIT DESCRIPT(ON INTR, pin 10 (interrupt request). If this input line is brought high, and the interrupts are not disabled through software, the CPU completes its current cycle and then processes the interrupt. (See "Interrupt Circuits" for more details.) INTA, pin 11 (interrupt acknowledge).
Page 64 Page 2.26 CIRCUIT DESCRIPTION (PC i 1)H AH-A)S P CH (HIGH ORDER AD DR E SS 10 PORT 10 PORT P C+ + I ADD T (LOW ORDER DATA FROM DATA FROM MEMORY DATA TO MEMORY ADDRESS) (I/O PORT ADDRESS) MEMORY OR PERIPHERAL (INSTRUCTION)
Page 65 Page 2.27 CIRCUIT DESCRIPTION From time T2 to T3, RD goes low and the instruction in the memory location pointed to by the address latches is placed on lines ADO-AD7, which are now acting as data lines. The data, which consists of an OUT instruction, is loaded into the Computer for internal processing during time T3 to T4.
Page 66 Page 2.28 CIRCUIT DESCRIPTION The 8088 CPU General The 8088 CPU is the Comupter's 16-bit processor, which is located at U211 on the schematic. This IC combines the re- sources of a 16-bit microprocessor's internal architecture with the easy-to-use 8-bit bus interface. In fact, most of the func- tions of the bus lines in the 8088 are identical to the 8085 at U210.
Page 67 Page 2.29 CIRCUIT DESCRIPTION Pin-Out Description Refer to Pictorial 2-8 while you read the following paragraphs. (4+N WAIT I-TCY (4'N WAIT)-' CY T wAIT TwAO GOES INACTIVE IN THE STATE JUST PRIOR TO T4 A(g-AIG A(g-AIS ST-S3 AODR/STATUS AOOR AIS AB AIS AB BUS R E SERVEO O AOOP/DATA...
Page 68 Page 2.30 CIRCUIT DESCRIPTION RD, pin 32 (read strobe). This line goes low when the CPU reads from memory or an I/O port, and goes to a high impe- dance state during hold acknowledge (HLDA). WR, pin 29 (write strobe). This line goes low when the CPU writes to memory or an I/O port, and goes to a high impedance state during HLDA.
Page 69 Page 2.31 CIRCUIT DESCRIPTION NMI, pin 17 (non-maskable interrupt). A positive-going transition on this line interrupts the CPU. It cannot be blocked with software. The CPU will complete its current instruction and then service the interrupt. INTR, pin 18 (interrupt request). The CPU tests this line during the last clock cycle of each instruction to see if some device is requesting an interrupt.
Page 70 Page 2.32 CIRCUIT DESCRIPTION MN/MX, pin 33 (minimum/maximum). A logic 1 on this pin places the 8088 in the minimum mode, the mode used by the Computer. When it is placed in the maximum mode, some of the pin functions change. Usually, the maximum mode is used for larger systems and multiprocessing systems.
Page 71 Page 2.33 CIRCUIT DESCRIPTION Processor Swap Port General The processor swap port controls which CPU is to be active, handles interrupt routing, and ensures proper timing of the clock circuits during the swap. To access the swap port, the CPU writes a control byte to port OFEH. Only three bits of the byte are used: ADO controls the automatic wrap and/or mask mode, AD1 controls the swap interrupt line, and AD7 performs the processor swap.
Page 72 Page 2.34 CIRCUIT DESCRIPTION The HOLD* line at U185 pin 11 asserts whenever a board on the S-100 bus takes control of the Computer. This causes U186 to disable both the 8085 and the 8088 through U187. Both CPUs respond by returning their HLDA signals; the 8088 at U186 pin 3 and the 8085 at U171 pin 2.
Page 73 Page 2.35 CIRCUIT DESCRIPTION 88 SEL U188-01 U188-Q2 U188-02 U188-03 U188- C K U 2D3-8 U203-11 85 HOLD 88 HOLD Pictorial 2-9 Switching from 8085 to 8088 The two top waveforms are the respective clocks for the 8085 and 8088 CPUs. These are present at the inputs of inverters U200 pin 2 and U200 pin 14.
Page 74 Page 2.36 CIRCUIT DESCRIPTION When Q2 goes high, it 3-states U200 through the exclusive- OR gate at U203B. At the same time, Q2 goes low to couple the 884 clock to the S4 line. Since, in this example, the two clocks are nearly 180 degrees out of phase, the clock im- mediately returns to 0, causing the spike at D in Pictorial 2-9.
Page 75 8085) line. This line is a "not-to-be-defined" line that can be used for any function by the computer manufacturer. For the H/Z-100 Series Computer, this line asserts when the 8088 is active. The same process takes place when control of the system is switched from the 8088 to the 8085;...
Page 76 Page 2.38 CIRCUIT DESCRIPTION If, while the 8085 is selected, the MSK line is set to logic 0, then U220 pin 2 disables U189A and U189D. This blocks the interrupt request from both the 8085 and the 8088. How- ever, if either a standard or an NMI interrupt request occurs, U156 pin 6 will go high to assert the NMINT line.
Page 77 Page 2.39 CIRCUIT DESCRIPTION At the same time, the CPU also writes the correct control bits to 8SEL and MSK on the processor swap port. The Com- puter changes CPUs, finds that the SWAPINT line is asserted, and jumps to the correct location to process the interrupt. Reset Circuits Power-Up Reset R114 and C189 provide the power-up reset signal for the...
Page 78 Page 2.40 CIRCUIT DESCRIPTION Keyboard Reset When you press the CRTL key and the RESET key at the same time, pins 8 and 9 of U103 go low and force U183 pin 10 to logic 1. This is inverted at U183 pin 4 and coupled to U185A through the filter network, R109 and C174.
Page 79 Page 2.41 CIRCUIT DESCRIPTION S-100 Bus Status Circuits The IEEE-696 S-100 bus contains eight status lines, because there are eight basic types of machine cycles. The Computer uses all but one of these lines. The unused line, sXTRQ is still available for use by plug-in boards. Following the S-100 (proposed IEEE-696) standard, the status lines designations are prefixed with a lower-case "s."...
Page 80 Page 2.42 CIRCUIT DESCRIPTION sM1, pin 44 (op code fetch). This line asserts when the 8085 processor fetches a new instruction from program memory. It returns to logic 0 at the end of the M1 machine cycle. How- ever, when the 8088 is operating, the asserted sM1 line does not guarantee the fetch of a new instruction.
Page 81 Page 2.43 CIRCUIT DESCRIPTION 88SEL also 3-states 85SO and 85S1 at pins 1 and 4 of U237. The line from 85IO/M is in a high-impedance state when the 8085 is disabled, so it does not need a buffer. U226 decodes the machine cycle status and asserts the cor- rect line on the output.
Page 82 Page 2.44 CIRCUIT DESCRIPTION Wait Timing The WAIT line at pin 9 of U226 equalizes the timing character- istics between the 8085 and the 8088. It does this by adding the appropriate wait states during a memory or I/O access. The number of wait states depends on the active CPU and the type access, as shown in the chart below.
Page 83 Page 2.45 CIRCUIT DESCRIPTION If either RDY or XRDY should go low, U205 pin 9 remains at logic 0 during that bus cycle. This causes the CPU to go into a wait state at the end of the cycle. (See the 8085 and 8088 data sheets in Appendix C for the exact timing relation- ships.) To see how the Computer uses the RDY line, refer to the "Video Board"...
Page 84 Page 2.46 CIRCUIT DESCRIPTION Inverted pSYNC couples from U219 pin 8 to U234 pin 12, and inverted system clock connects to U234 pin 11. Between state T1 and T2, the inverted pSYNC is logic 0. The rising edge of S4 latches this onto U234 pin 9, which is buffered through U180B to form the pSTVAL* signal.
Page 85 Page 2.47 CIRCUIT DESCRIPTION pWR*, pin 77 (valid write data). This is a generalized write strobe that writes data from the data bus into memory or an output port. It is timed with pSYNC and pSTVAL* to ensure that the data is valid on the DO bus before a write takes place. The CPU write command is inverted through U220 pin 12 and applied to U235 pin 13, a three-input NAND gate.
Page 86 Page 2.48 CIRCUIT DESCRIPTION Memory Memory Control Latch The memory control latch, U176, determines the addressing of RAM and ROM. It also sets the status of the parity circuits. The CPU accesses this latch by writing the correct byte to port OFCH.
Page 87 Page 2.49 CIRCUIT DESCRIPTION Dynamic RAM The Computer uses 64K x 1 bit dynamic RAM chips for main memory. There is one IC per bank per bit position, so that eight ICs make u p 6 4 k b ytes. For th e f irst 64K b ank, U109 = MDO and U102 = MD7.
Page 88 Page 2.50 CIRCUIT DESCRIPTION Address Multiplexer The address multiplexers consist of U146 and U128. These ICs couple the lower eight bits of the 16-bit address bus to MAO-MA7 during RAS time. They next pass the upper eight bits during CAS time. Multiplexing permits keeping the pin count down on the RAM ICs.
Page 89 Page 2.5't CIRCUIT DESCRIPTION Memory Map Decoder The memory map decoder is made up of U111, U110, and U173. It performs three major functions: {1) decodes the ad- dress bus to select the correct 64K bank, (2) provides read/ write control lines for the RAM and the data bus, and (3) per- forms correct addressing and control during refresh.
Page 90 page 2.52 CIRCUIT DESCRIPTION The three row-enable lines connect to pins 1, 2, and 3 of the PAL at U110. This IC decodes these, and other inputs, to assert RAS, CAS, WE, and MDGATE at the appropriate times. Basically, RAS asserts under the Boolean condition: RASn *TAP1 *RREQ) + (BCYC ) .
Page 91 page 2.53 CIRCUIT DESCRIPTION REF2 REF3 SYNC SYNC U130-6 U130-6 MEMR MEMR BSEL RE ER U154-5 U154-5 RDREQ ROREQ U170-6 UI70-6 TA P1 TA P1 TA P2 TAP2 60'/R 8 0'/R ouTIui44-8) OUT(U144-8) CLRMR C LRNIR U151-12 U151-12 RREQ RREQ BCYC BCYC CLRRR...
Page 92 Page 2.54 CIRCUIT OESCRIPTION The memory location pointed to by the address is now written to or read from the CPU. The two remaining outputs of U110 are the write-enable line at pin 13 and the memory data gate at pin 12. Write-enable asserts whenever there is a memory write during a bus cycle at TAP1 or TAP2 time.
Page 93 Page 2.55 CIRCUIT DESCRIPTION Refresh Circuits The refresh circuits consist of a refresh clock, U147-U148; the refresh request circuit, U152; memory request, U167; tim- ing and control ICs U144 and U150; control circuits to the CPU, U168-U158, U150, and U165; and the refresh address generator, U127 and U126.
Page 94 Page 2.56 CIRCUIT DESCRIPTION the signal so that BCYC (bus cycle active) at U150 pin 9 cannot change to its BCYC state until memory read is com- pleted. This is explained in more detail later. If, however, no memory read or write is taking place during the refresh request, the logic 0 at U150 pin 12 is latched into U150 pin 9 on the next positive-going signal from U159 pin 3.
Page 95 Page 2.57 CIRCUIT DESCRIPTION MDENB asserts only when the CPU is attempting to access the on-board dynamic RAM. If the CPU is accessing a memory board on the S-100 bus, it will not affect the on-board RAM, so there is no need to put the CPU in a wait state during refresh.
Page 96 Page 2.58 CIRCUIT DESCRIPTION Now, assume that a refresh request occurs during the read cycle previously discussed. U148 pin 9 in the request circuits latches high. Also, U151 pin 13 is high since this is not a write operation. However, SYNC is low during the first part of the bus cycle, so U151 pin 12 is low.
Page 97 Page 2.59 CIRCUIT DESCRIPTION As described before, if the CPU attempts to read or write the onboard memory during this time, MDENB will go high and force RDY low, generating a wait state. After REFWAIT goes low, RDY goes high, allowing a normal bus cycle to occur.
Page 98 Page 2.60 CIRCUIT DESCRIPTION Number of inputs that are high. Outputs E ven O d d 0, 2 , So if there is an odd number of high bits in the data byte, the logic 1 on pin 4 of U153 makes the number even. U153 pin 5 responds by going high.
Page 99 Page 2.61 CIRCUIT DESCRIPTION 1 and asserts the S-100 ERROR* line at U158 pin 6. This generates an error interrupt at U208 pin 18. From here, it is up to the user's software to process the interrupt. When KILPAR is asserted, U152 is held clear to prevent a parity error interrupt.
Page 100 Page 2.62 CIRCUIT D E S C R IPTION Mode 0 is the default configuration, in which memory is con- tiguous from 0 to 192K. In mode 1, the first 48K of bank 0 appears to be swapped with the first 48K of bank 1. The two 16K areas, and the rest of RAM, are unchanged.
Page 101 Page 2.63 CIRCUIT DESCRIPTION System Monitor ROM Addressing The monitor ROM (U190) controls the operation of the Com- puter after power-up reset or hard reset. It initializes the nec- essary I/O ports and determines which CPU will be active in the monitor mode. Though currently 8K, jumpers J101 and J102 allow you to expand this ROM to 32K.
Page 102 Page 2.64 CIRCUIT DESCRIPTION The 8088 selects the next operating mode by latching PROM1 to logic 1 and leaving PROMO at logic 0. U190 is now located in the top 8K of the 8088's natural 1 Mbyte address space. This is the location that the ROM is normally in while the Computer is in the monitor mode.
Page 103 Page 2.65 CIRCUIT DESCRIPTION Address/Data Circuits General Please refer to Pictorial 2-12 while you read the following para- graphs. As stated in the discussions on the 8085 and the 8088, the address and data lines of these CPUs are multiplexed onto the same bus.
Page 104 Page 2.66 CIRCUIT DESCRIPTION Address Latches At the beginning of clock cycle T1, the 8088 asserts the 88ALE line at U211 pin 25. This signal couples through the OR gate at U221 pin 1 to pin 11 of U197 and U196, which are two 3-state, octal, D-type latches.
Page 105 Page 2.67 CIRCUIT DESCRIPTION Data Latches If the CPU is writing data, either to memory or to an output port, it asserts the WR line at U211 pin 29. This signal is inverted by U220 pin 12 to form the CPUWR control signal. CPUWR connects to U198 pin 11 and holds this latch transpa- rent as long as it is high.
Page 106 Page 2.68 CIRCUIT DESCRIPTION Extended Addressing The extended addressing circuits; U193, U212, and U213; maintain S-100 compatibility by making it possible for the CPU to address up to 16 Mbytes of memory. When the 8088 is active, U193 pin 1 is high and couples PA16-PA19 to pins 3, 4, 7, and 8 of U213.
Page 107 Page 2.69 CIRCUIT DESCRIPTION Interrupt Circuitry General Maskable interrupts are routed through the IC at U208, an 8259A programmable interrupt controller (PIC). This IC fea- tures an 8-level priority controller and programmable interrupt modes that allow using this IC with either the 8085 or the 8088.
Page 108 Page 2.70 CIRCUIT DESCRIPTION As previously mentioned, U208 is the master PIC and handles all of the main board and video board interrupts. These inter- rupts are shown in the chart below in order of priority (highest first). Level ~ Descri ticn ERRORINT: Parity error or S-100 pin 98 (error line).
Page 109 Page 2.71 CIRCUIT DESCRIPTION If the 8085 is active, the following sequence occurs: Th e CPU asserts the INTA line at pin 26 (of 8259A). U2 0 8 p l aces the 8080/8085 CALL instruction (OCDH) onto the data bus at pins 4 through 11. T he 8 085 decodes this call instruction and determines that it requires two more bytes.
Page 110 Page 2.72 CIRCUIT DESCRIPTION Th e C P U multiplies the type number by four to find the correct location in the vector table. The C P U saves its current location in stack and loads the addressed vector table data into the code segment register and instruction pointer.
Page 111 Page 2.73 CIRCUIT DESCRIPTION Nonmaskable Interrupt Sequence The nonmaskable interrupt cannot be blocked by software. When the rising edge of the NMI pulse is present at the CPU, the processor must finish its current instruction and service the interrupt request. The NMI circuits consist of U156C, U156B, and surrounding components.
Page 112 Page 2.74 CIRCUIT DESCRIPTION Interrupt Routing The dual-D flip-flop at U202 retimes the maskable interrupt and applies it to U189A and U189B. If the 8085 is the active CPU, U189A couples the interrupt request to U210 pin 10. If the 8088 is active, U189B routes the request to U211 pin If an NMI occurs while the 8085 is active, U189D sends it to the TRAP input at U210 pin 6.
Page 113 Page 2.75 CIRCUIT DESCRIPTION Keyboard Keyboard General The keyboard circuits are designed around the 8041A univer- sal peripheral interface (UPI) at U204. This IC is a dedicated 8-bit microcomputer with internal RAM and ROM. The RAM is 64 x 8 bits while the ROM is 1024 x 8 bits. The pin-out of the 8041A is described in the following para- graphs.
Page 114 Page 2.76 CIRCUIT DESCRIPTION XTAL1 and XTAL2, pins 2 and 3 (clock lines). These lines provide a 6-MHz crystal-controlled clock to the circuits inside the UPI. P10-P17, pins 27-34 (keyboard row input). These bidirec- tional I/O lines are programmed as input lines. They connect to ROWO-ROW7 of the Computer's matrix keyboard.
Page 115 Page 2.77 CIRCUIT DESCRIPTION The combination of these four lines effectively turns U199 and U184 into a 4-to-16 line decoder. When the UPI causes these lines to count up from binary 0 to binary 15, each column pulses low once, starting at column 0 and ending at column 15.
Page 116 Page 2.78 CIRCUIT DESCRIPTION Timer and E-Clock Timer and Clock Timer The timer circuit is designed around the 8253-5 programmable interval timer IC at U160. The 8253-5 consists of three counters, a data buffer bus, read/ write logic, and a control word register. The counters are 16-bit down-counters with separate clock inputs, gate inputs, and outputs.
Page 117 Page 2.79 CIRCUIT DESCRIPTION Interrupt on Terminal Count. The output goes to logic 1 when the counter reaches 0 (terminal count). Programmable One-Shot. Not used since the gate lines are tied to logic 1. Rate Generator. This is a divide-by-n counter. The output goes low for one clock period, returns high, and counts down the number stored in the counter.
Page 118 Page 2.80 CIRCUIT DESCRIPTION The timer is clocked from CNTRCLK, a 250-kHz clock from U192 pin 11. This signal is parallel-connected to the inputs of counter ¹ 0 and counter ¹ 2 a t p ins 9 and 18 of U160. The output of counter ¹0 at pin 11 of U160 couples to the interrupt status latch at pin 11 of U112, and to the input of counter ¹1 at U 160 pin 15.
Page 119 Page 2.81 CIRCUIT DESCRIPTION E-Clock The E-clock logic retimes the S-100 clock and control signals to the values required by the video board and I/O circuits. The timing diagram in Pictorial 2-13 and the following section explains how this is done. U224 pin 3 forms the STVAL*SYNC signal during bus cycle 2.
Page 120 Page 2.82 CIRCUIT DESCRIPTION I/O Circuitry Serial Ports A and B General The two serial ports permit the Computer to communicate with external devices such as printers, MODEMs, plotters, and voice synthesizers. This frees the S-100 slots on the main board for other purposes.
Page 121 Page 2.83 CIRCUIT DESCRIPTION When it selects one of these ports, it asserts EPCIACS from the I/O port decoder and CSEN from the E-clock logic. These lines connect to pins 1 and 2 of U174 and assert the chip-ena- ble line (pin 11) of U243. Also, the CPU asserts pins 12 and 10 to select the right inter- nal register.
Page 122 Page 2.84 CIRCUIT DESCRIPTION In the receive mode, serial data enters the EPCI at pin 3 through U247D, which converts the + or — 12-volt RS-232 levels to TTL levels. The EPCI extracts the data bits and loads it into the receive data holding register. The RxRDY line then goes low to interrupt the CPU through U222, pin 10.
Page 123 Page 2.85 CIRCUIT DESCRIPTION Serial Port B Serial port B consists of U242 and its surrounding circuitry. This port is a DTE port and can be used to connect to devices such as a MODEM or to another computer. To select this IC, the CPU addresses the following ports: OECH Rec e i ver holding register (read).
Page 124 Page 2.86 CIRCUIT DESCRIPTION Parallel Port General The parallel port is designed around a 68A21 peripheral inter- face adapter (PIA) at U114. This IC performs three functions: (1) it operates as a printer port; (2) it serves as a port for a light pen;...
Page 125 Page 2.87 CIRCUIT DESCRIPTION Printer Port The printer port is a parallel output port with handshaking capabilities. It allows you to connect the Computer to some of the more popular printers without having to pay extra for a serial interface. The parallel data leaves U114 at PAO, PA1, and PB2 through PB7 and couples through U115 to J3 w here it becomes PDATA1 through PDATA8.
Page 126 Page 2.88 CIRCUIT DESCRIPTION To see when the BUSY line goes to the inactive state, it moni- tors the logic level of PAO. This simplifies programming since, otherwise, CB2 must be programmed to respond to the oppo- site-polarity signal transition. The CPU uses the INIT line to initialize some printers.
Page 127 Page 2.89 CIRCUIT DESCRIPTION pin 40 causes IRQA at pin 38 of U114 to go low if unmasked by software. IRQA is then inverted by pin 13 of U134 to cause a display interrupt at the CPU. When the CPU acknowledges the interrupt, it must assert the 6821CS line (from the I/O decoder port) at U175 pin 4.
Page 128 Page 2.90 CIRCUIT DESCRIPTION I/O Port Decoder T he heart of the I/O port decoder is U179, a 256 x 4 b i t PROM. Depending on which main board port the CPU addres- ses, U179 enables U159 or U157, respectively a 3-to-8 line decoder and a dual 2-to-4 line decoder.
Page 129 Page 2.91 CIRCUIT DESCRIPTION If U179 pin 11 is asserted, section A of decoder U157 is selected. It decodes address lines BA1 and BA2 to enable t he interrupt ports, 8259ACSS and 8 2 59ACSM, or t h e keyboard port, KEYBDSEL. If U179 pin 10 is asserted, section B of decoder U157 is selected.
Page 130 Page 2.92 REPLACEMENT PARTS LIST Description C IRCUIT H E A T H Comp. No. Part No. Resistors All resistors are 1/4 W, 5%, unless marked otherwise. R101-R103 6-472-12 4700 tt R104 6-102-12 1000 0 R105 6-6651-12 7150 tt, 1% R106 6-6811-12 68100, 1%...
Page 131 page 2.93 REPLACEMENT PARTS LIST CIRCUIT HEATH Description Comp. No. Part No. Capacitors All capacitors are 20%, unless marked otherwise. C101-C113 21-762 .1 tLF ceramic 25-918 100 tLF electrolytic C113-1 C114,C115 21-762 .1 p.F ceramic 470 pF ceramic C116-C118 21-773 21-762 .1 tjj.F ceramic C119...
Page 132 Page 2.94 REPLACEMENT PARTS LIST CIRCUIT H E AT H Descr i ption Comp. No. Part No. Inductors L101-L104 235 - 22 9 35 B, H Transducers 473-29 X101 Audio Transducer Crystals 404-645 10 MHz Y101 Y102 404-647 6 MHz 404-644 15 MHz Y103...
Page 133: Semiconductor Identification
Page 2.95 SEMICONDUCTOR IDENTIFICATION This section is d ivided into four parts. The "Component Number Index" relates circuit component numbers to Heath part numbers. The "Part Number Index" relates part numbers to manufacturers' part numbers, as well as providing lead con- figuration drawings for each part.
Page 134 page 2.96 SEMICONDUCTOR IDENTIFICATION CIRCUIT HEATH COMPONENT PART NUMBER NUMBER U162-U163 443-791 U164 443-754 U165 443-752 443-872 U166 U167 443-900 443-875 U168 443-976 U169 443-1081 U170 443-1051 U171-U172 444-130 U173 U174 443-875 443-797 U175 443-879 U176 443-754 U177 443-791 U178 444-101 U179 443-857...
Page 135 page 2.97 SEMICONDUCTOR IDENTIFICATION HEATH CIRCUIT COMPONENT PART NUMBER NUMBER 443-791 U217 443-1112 U218 U219 443-900 U220 443-755 U221 443-875 443-728 U222 443-791 U223 U224 443-1048 U225 443-1049 444-105 U226 443-837 U227 U228 442-644 U229 442-646 U230 443-795 443-74 U231 U232 442-53 U233-U234...
Page 136 page 2.98 SEMICONDUCTOR IDENTIFICATION Part Number Index DESCRIPTION LEAD CONFIGURATION HEATH MAY BE REPLACED (TOP VIEW) PART WITH NUMBER DL14-CB201 41-10 200 nS delay line 56-89 GD510 IMPORTANT; TNE OANDKO END OF DIODES CAA OK MARRED IN A NOMOER OF WAYS. 1N4149 56-56 Diode...
Page 137 page 2.99 SEMICONDUCTOR IDENTIFICATION Part Number Index (cont'd) DESCRIPTION LEAD CONFIGURATION MAYBE HEATH (TOP VIEW) REPLACED PART NUMBER WITH Open Collector 443-72 7417 Hex Suffers Peripheral Drivers 443-74 75452 443-728 74LSOO Quad 2-input NAND CLOC K CLR c< CK CLR 443-752 74LS175 Quad D flip-flop...
Page 138 page 2.100 SEMICONDUCTOR IDENTIFICATION Part Number Index (cont'd) MAY BE DESCRIPTION LEAD CONFIGURATION HEATH (TOP VIEW) PART REPLACED NUMBER WITH I YI I Y2 ZA I I Y3 I Y4 3-state octal Buffer 74LS240 IA I I A2 2Y 3 IA 3 I A4 2Y I...
Page 139 Page 2.1 01 SEMICONDUCTOR IDENTIFICATION Part Number Index (cont'd) HEATH MAY BE DESCRIPTION LEAD CONFIGURATION REPLACED PART (TOP VIEW) NUMBER WITH I YI 2 A3 2 A2 I Y 4 2A I 443-791 74LS244 3-state buffer/driver 2 A 4 IA2 2 YI G ND + 12V 4 8...
Page 140 Page 2.102 SEMICONDUCTOR IDENTIFICATION ont'd) Part Number Index (c HEATH MAY BE DESCRIPTION LEAD CONFIGURATION PART REPLACED (TOP VIEW) NUMBER WITH Vcr. CLO CK (. K (. K CI EAR CII AR CLEAR Cl I Ak 443-805 74LS273 Octal 2-113put D flip-flop CLEAR CIEAR...
Page 141 Page 2.103 SEMICONDUCTOR IDENTIFICATION Part Number Index (cont'd) HEATH MAY BE DESCRIPTION LEAD CONFIGURATION PART REPLACED (TOP VIEW) NUMBER WITH 443-857 74LS367 Hex 3-state buffer GN D Vcc. 443-864 74LS11 Triple 3-input AND G i s D Schmitt Trigger 443-872 74LS14 Hex inverter Gi x D...
Page 142 Page 2.104 SEMICONDUCTOR IDENTIFICATION Part Number Index (cont'd) HEATH DESCRIPTION MAY BE LEAD CONFIGURATION PART REPLACED (TOP VIEW) NUMBER WITH DATA OUli'UTS Decoder 443-877 74LS138 OUTPUT ENABlE SELECT 40 C LOCK V cc D CK C1EAR CLEAR CLEAR Hex D flip-flop 443-879 74LS174 LEAR...
Page 143 page 2.105 SEMICONDUCTOR IDENTIFICATION Part Number Index (cont'd) MAY BE DESCRIPTION HEATH LEAD CONFIGURATION PART REPLACED (TOP VIEW) NUMBER WITH 2 P R CLR 2 CK K CLR 0 74LS112 Dual J-K flip-flop 443-948 P R Q K CLR GN D I PR C A S 64K x 1 RAM...
Page 144 Page 2.106 SEMICONDUCTOR IDENTIFICATION Part Number Index (cont'd) HEATH MAY BE LEAD CONFIGURATION DESCRIPTION PART REPLACED (TOP VIEW) NUMBER WITH 1 iNPUTS Odd/even parity check 443-1001 74LS280 EVEN ODD INPUT EVE!'! ODD INPUTS OUTPUTS 4 0 39 38 3 7 3 6 3 5 3 4 3 3 32 31 30 2 9 2 8 27 26 2 5 2 4 Microprocessor...
Page 145 Page 2.107 SEMICONDUCTOR IDENTIFICATION Part Number Index (cont'd) HEATH MAY BE LEAD CONFIGURATION PART REPLACED DESCRIPTION (TOP VIEW) NUMBER WITH >« Clock Generator/driver 443-1011 8284 r« 28 2 7 2 6 25 Programmable 8259A 443-1012 8259A Interrupt controller « I «...
Page 146 Page 2.108 SEMICONDUCTOR IDENTIFICATION Part Number Index (cont'd) DESCRIPTION HEATH MAY BE LEAD CONFIGURATION PART REPLACED (TOP VIEW) NUMBER WITH ' CC 443-1034 74LS38 Quad NAND buffer G ND SELECT OUTPUTS DATA STRB INPUT 443-1036 74LS156 Dual 2 to 4 decoder DATA STRB SELECT IY3 I YO G N D...
Page 147 Page 2.109 SEMICONDUCTOR IDENTIFICATION Part Number Index {cont'd) HEATH MAY BE DESCRIPTION LEAD CONFIGURATION PART (TOP VIEW) REPLACED NUMBER WITH 443-1045 74ALS02 Quad 2-input NOR 74ALS10 443-1047 Triple 3-input NAND G N >D Quad NOR buffer 443-1048 74ALS28 Quad 2-input 443-104g 74ALS37 NAND buffer...
Page 148 Page 2.110 SEMICONDUCTOR IDENTIFICATION Part Number Index (cont'd) MAY BE HEATH LEAD CONFIGURATION DESCRIPTION REPLACED PART (TOP VIEW) WITH NUMBER V CC 2 C L R 2D 443-1051 74ALS74 Dual D flip-flop C K CLR 1 CLR I CK I PR OUTPUTS R I PPLE CARRY...
Page 149 74ALS1020 NAND buffer Ci ' U D Multivibrator 443-1112 9602 Cx I 28 27 2 6 2 5 21 20 1 9 18 444-87-2 Available 8K Monitor ROM only from Zenith Data Systems or Heath Company 1 0 11 (cont'd)
Page 150 REPLACED (TOP VIEW) NUMBER WITH 2 8 2 7 2 6 25 444-87-5 Available only from Monitor ROM Zenith Data Systems or Heath Company CS2 C S ] 444-101 Available System I/O Decoder ROM only from Zenith Data Systems or...
Page 151 DESCRIPTION PART REPLACED (TOP VIEW) NUMBER WITH PAL12H6 444-128 Available HAL or only from PAL12H6 Zenith Data Processor swap control Systems or Heath Company AND GATE ARRAY PAL16L2 444-1 29-1 Available HAL or only from PAL16L2 Zenith Data ROM address decoder...
Page 152 Page 2.114 SEMICONDUCTOR IDENTIFICATION Pal Equations 444-126/RAM Controller REN2 RENl RASO REND RAS1 TAP1 c RAS2 TA P2 Vc, CAS-A CAS- B BCYC C A S- C RREQ MD GATE GND 8 PHANTOM LOGIC EQUATIONS RENO *TAP1 + R E NO * RREQ + BCYC *TAP1 RASO *STC...
Page 153 page 2.115 SEMICONDUCTOR IDENTIFICATION 444-128/Hold of Dual Processors 8 VCC 88HOLD 88HLDA LU 85HLDA pHLDA 8SEL 88SEL INOU3 O U T3 INOU2 OUT2 85HOLD HOLD GND F LOGIC EQUATIONS SS HOLD 85HLDA + SSEL + INOU3 * HOLD + HO L D *SSEL *88HLDA 85HLDA...
Page 154 page 2.116 SEMICONDUCTOR IDENTIFICATION 444-129-1/Top 32K Selector MEMR ROM1 A16 u ROMSEL A17 ~ g ROMO ~ A2 1 GND p LOGIC EQUATION * ROM1 + M E M R *ROMO *ROM1 *A15 ROMSEL = M E M R * R O M O * ROMO*RO M 1 * A15*A16 *A 1 7 * A18*A19 * A 2 0 * A 2 1 *A22*A23 + MEMR...
Page 155 Page 2.117 SEMICONDUCTOR IDENTIFICATION 444-130/High Address Decoder BA18 BA19 BCYC g TAP2 BA20 BA21 a DEC ODEN <V, CLRRR BA22 BA23 CLRMR MA PSELO D I E N u P HANTOM MAPSEL1 MDENB TA P1 GND o DBIN LOGIC EQUATIONS DECODEN *BA23 = B A 1 8 * B A 1 9 * B A 2 0 * BA21 *BA 2 2...
Page 156 page 2.118 SEMICONDUCTOR IDENTIFICATION ROM Codes title IODEC I/O decoder for the Z-100 ZDS par t n o . : 444-101 r el e ase d a t e : 5/25/ 82 prom: 82s 129 (256x4 ) checksum: Oe57 0000' cseg .
Page 157 Page 2.119 SEMICONDUCTOR IDENTIFICATION d ecoder f o r t h e Z -1 0 0 IODEC j:/0 0023 0024' 0025' 0026' 0027 0028' 0029' 002A' 002B' 002C' 002D' 002E' 002F ' 0030' 0031 0032' 0033' 0034' 0035' 0036' 0037' 0038' 0039' 003A...
Page 158 page 2.120 SEMICONDUCTOR IDENTIFICATION d ecoder f o r t h e Z -1 0 0 IODEC I/0 0051 ' 0052 ' 0053 ' 0054' 0055' 0056' 0057' 0058' 0059' 005A' 005B' 005C' 005D' 005E' 005F' 0060' 0061' 0062' 0063' 0064' 0065' 0066'...
Page 159 page 2.121 SEMICONDUCTOR IDENTIFICATION d ecoder f o r t h e Z -1 0 0 IODEC I/O 007F ' 0080' 0081 0082' 0083' 0084' 0085' 0086' 0087r 0088' 0089' 008A' 0088' 008C' 008D' 008E' 008F' 0090' 0091 0092' 0093' 0094' 0095' 0096...
Page 160 page 2.122 SEMICONDUCTOR IDENTIFICATION IODEC I/O d ecoder f o r t he Z -1 0 0 OOAD' ; Reserved f o r Z -2 0 7 ; Reserved f o r Z -2 0 7 OOAE Z - 2 0 7 OOAF' ;...
Page 161 page 2.123 SEMICONDUCTOR IDENTIFICATION IODEC 1/0 decoder for the Z-100 O ODB' ; Vide o 6 8 a 2 1 po r t O ODC' ; Vide o 6 8 a 4 5 C R T C D ODD' ; Vide o 6 8 a 4 5 CR T C O ODE' ;Video light pen counter...
Page 162 page 2.124 SEMICONDUCTOR IDENTIFICATION d ecoder f o r t he Z -1 0 0 IODEC I/O OOEO' ; 68a21 Pr i n t e r p o rt OOE1 ; 68a21 Pr i n t e r p o r t OOE2 ' ;...
Page 163 page 2.125 SEMICONDUCTOR IDENTIFICATION IODEC E/0 decoder for the Z-100 Macros: Symbols: No F a t a l er r or ( s )
Page 164 page 2.f 26 SEMICONDUCTOR IDENTIFICATION MEMDEC — MEMORY MAPPING ROM Z DS part n o . : 4 44- 10 4 release date: 5 / 2 5/82 p rom: 82 s 1 2 9 ( 2 5 6 x 4 ) checksum: 074 0 ORG OOH...
Page 165 Page 2.127 SEMICONDUCTOR IDENTIFICATION OOOC' OOOD OOOE' OOOF' 0010 ' 0011 ' 0012 ' 0013' 0014 ' 0015 ' 0016' 0017 ' 0018' 0019 ' 001A ' 001B ' 001C ' 001D ' 001E ' 001F ' 0020' 0021 0022 0023' 0024' 0025...
Page 166 page 2.128 SEMICONDUCTOR IDENTIFICATION 0037 0038' 0039 003A' 003B 003C' 003D ' 003E' 003F' • %%%%% % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % MAP 1 •...
Page 167 page 2.129 SEMICONDUCTOR IDENTIFICATION 005E' 005F' 0060' 0061 0062' 0063' 0064' 0065' 0066' 0067' 0068' 0069' 006A' 006B' 006C' 006D' 006E' 006F' 0070' 0071' 0072' 0073' 0074' 0075' 0076' 0077' 0078' 0079' 007A 007B' 007C 007D' 007E' 007F' • %%%%% % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % HAP 2 •...
Page 168 Page 2.130 SEMICONDUCTOR IDENTIFICATION 0084' 0085' oO86 0087' 0088' 0089' 008A 008B' 008C' 008D 008E' 008F' 0090 ' 0091 ' 0092 ' 0093' 0094' 0095' 0096' 0097' 0098' 0099' 009A 009B' 009C' 009D 009E' 009F OOAO OOA1 ' OOA2' OOA3' OOA4' OOA5' OOA6'...
Page 169 Page 2.131 SEMICONDUCTOR IDENTIFICATION OOBO' OOB1 ' OOB2' OOB3 OOB4' OOB5' OOB6' OOB7' OOB8' OOB9' OOBA' OOBB' OOBC' OOBD' DOBE OOBF • %%%%% % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % HAP 3 •...
Page 170 page 2.132 SEMICONDUCTOR IDENTIFICATION OOD5' OOD6' OOD7' OOD8' OOD9 OODA' OODB' OODC' 6pDD' OODE' OODF' OOEO' OOE1 ' OOE2' OOE3' OOE4' OOE5 OOE6' OOE7' OOE8' OOE9r OOEA' OOEB' OOEC OOED' OOEE' OOEF' OOFO' OOF1 ' OOF2 ' OOF3 OOF4 ' OOF5 ' OOF6 OOF7 '...
Page 171 page 2.133 SEMICONDUCTOR IDENTIFICATION...
Page 172 Page 2.134 SEMICONDUCTOR IDENTIFICATION D ecode Rom fo r t h e Z - 1 0 0 title C P U S tatus ZDS part n o . : 444-105 r el e ase d a t e : 5/25/ 82 prom: 82s123(32xS) checksum:...
Page 173 page 2.135 SEMICONDUCTOR IDENTIFICATION ver. 2 CPU Status Decode Rom for the Z-100 88 sI NTA 001C 00000011b ; 03h 8 8 sI NP 00010001b ; 11h 0 01D ' 20h 88 sOUT 00100000b 0 01E ; 05h 88 sHLTA 0 01F 00000101b...
Page 174: Circuit Board X-Ray View
Page 2.136 CIRCUIT BOARD X-RAY VIEW NOTE: To find the PART NUMBER of a component for the pur- pose of ordering a replacement part: Fi n d the circuit component number (R5, C3, etc.) on the X-Ray View. Lo c ate this same number in the "Circuit Component Number"...
Page 175 CII O CIII C102 CI0 3 C1 0 4 C105 C1 0 6 C107 C I 8 C1 0 9 C 112 RIOI C113 PIS I C I 31 C166 C165 0 4l R108 C174 - I CI74 R109~ ~ C186 m + C Ik O 4.
Page 176 C114 R101 C115 C113 C119 P191 :C113-1 6131 'C198 U229 p p II I 0206 ok~~'W MAIN CIRCUIT BOARD Component side shown in red, foil side shown in gray.
Page 177 Page 2.137 INTERCONNECT PIN DEFINITIONS S-100 Bus Definitions The definitions of the S-100 bus pins are given in the Appendix A portion of this documentation. RS-232 Pin Definitions The following chart gives the definitions of the RS-232 Serial Port pins. RS-232C Interface Signals ~ Descri ticn Protective ground...
Page 178: Interconnect Pin Definitions
page 2.138 INTERCONNECT PIN DEFINITIONS Parallel Port Definitions The chart below gives the definition of the parallel port. Parallel Port Pinout FUNCTION SI GN AL NAME STROBE A pulse that clocks data. Data to the peripheral. P DATA1 Data to the peripheral. PDATA2 PDATA3 Data to the peripheral.
Page 179 Page 2.139 INTERCONNECT PIN DEFINITIONS Light Pen Definitions The following chart gives the definition of the light pen port. PIN S IGNAL NAM E FU N C T ION + 5V Plus 5-volt supply LT PNS W Monitors light pen switch LT PEN Light pen "hit"...
Page 180 Page 2.140 INTERCONNECT PIN DEFINITIONS Connector P107 PIN S IGNAL NAME FU N C T ION SHIFT ROW Shift row line CTRL/RESET Control (CTRL) and RESET line ROWO Row 0 line Row 1 line ROW1 ROW2 Row 2 line 4 5 6 7 ROW3 Row 3 line ROW4...
Page 181 Page 2.141 INTERCONNECT PIN DEFINITIONS Video Logic Board Connectors The following charts give the definitions of the video logic cir- cuit board connectors. Connector P104 P IN S I G N A L NAM E F U N C T I O N + 5VDC + 5-volt supply line + 5VDC...
Page 182 Page 2. l42 INTERCONNECT PIN DEFINITIONS Ground Ground BDOO BD01 Data output lines BD02 BD03 Ground Ground Ground Ground BD04 Data output lines BD05 BD06 BD07 Ground Ground BDIO BDI1 BDI2 Data input lines BDI3 BDI4 BDI5 BDI6 BDI7 RDBFRENBL Read buffer enable No connection Ground...
Page 183 Page 2.143 INTERCONNECT PIN DEFINITIONS STVAL*SYNC Status valid signal BMWRT Buffered memory write Status write Write strobe Chip-select line DBIN Data request control signal VI DINT Video Interrupt Ground Ground Ground Ground...
Page 184: Power Supply Connectors
page 2.144 INTERCONNECT PIN DEFINITIONS Power Supply Connectors The following charts give the definitions of the power supply connectors. FUNCTION PIN S IGNAL NAME Ground Ground No connection Plus 5-volt supply Plus 5-volt supply Plus 5-volt supply Plus 5-volt supply Ground Ground Connector P102...
Page 185: Description
Page 3.1 Keyboard Encoder Description User Options and Programming Theory of Operation Troubleshooting 3.10 Keyboard Scan Matrix 3.11 Encoder Output Codes (hex) 3.12 Keyboard Key Layout 3.19...
Page 186 Page 3.2 D ESC R IPT ION The keyboard encoder (or processor) scans the keyboard matrix to determine if a key has been pushed down. After finding a "down" key, it then sends a corresponding key code to the system to indicate which key is down. This is its normal ASCII mode of operation.
Page 187 Page 3.3 USER OPTIONS AND PROG R A M M ING Power Configuration After power-up or a hard reset, the keyboard encoder is in- itialized to the following state: • Au t o repeat is enabled. • Ke y click is enabled. •...
Page 188 Page 3.4 USER OPTIONS AND PROG R A M M ING Programming Specifications Command port address — F 5 (hex) F4 (hex) Data port address F5 (hex) Status port address I/O Protocol All I/O to the keyboard should obey the following rules. Output To Keyboard Encoder •...
Page 189 Page 3.5 USER OPTIONS AND PROG R A M M ING • Po l l ing — The KDA (Keyboard Data Available) bit of the status register will always be set when a key is placed on the data port. The bit is cleared when the data port is read. Input Status From Keyboard Encoder The status port may be read at any time without disturbing the operation of the keyboard.
Page 190: Command Summary
f age 3.6 USER OPTIONS AND PROG R A M M ING Command Summary COMMAND CODE (hex) Reset Autorepeat ON Autorepeat OFF Key click ON Key click OFF Clear FIFO Click Beep Enable keyboard Disable keyboard Event driven mode ASCII scan mode Enable Interrupts Disable Interrupts Command Definitions...
Page 191 Page 3.7 USER OPTIONS AND PROG R A M M ING CLEAR FIFO — Empties the keyboard processor's FIFO of any keys which may be in it. The data register of the keyboard en- coder is not cleared by this command. Only an input from the data port will clear it.
Page 192: Theory Of Operation
Page 3.8 THEORY OF OPERATION The keyboard encoder circuitry basically consists of a Univer- sal Peripehral Interface (UPI) microcomputer. (See the Partial Schematic.) It is a one-chip microcomputer that connects di- rectly to the master processor data bus. The main features of this device are: •...
Page 193: Theory Of Operation
Page 3.9 THEORY OF OPERATION I- $ 4I to n Jd 4 lo ' J J I 4 DJ t4 Jt I - IJ 0 d d O O- ; a d d t ' 0 IIJ. tJJg O IOQ 4 Otno ll N 4 t4...
Page 194 Page 3.10 TROUBLESHOOTING Use the following chart to help you identify the source of prob- lems. The chart lists conditions and possible causes for specific problems. If you cannot resolve the problem, refer to the war- ranty and service information supplied with your Computer. If you have electronics service skill, you may wish to service some problems yourself.
Page 195: Keyboard Scan Matrix
Page 3.11 KEYBOARD SCAN MATRIX Pictorial 3-1 shows the keyboard scan matrix; how the keys are positioned electrically. C> Pictorial 3-1 Keyboard Matrix...
Page 196: Encoder Output Codes
Page 3.12 ENCODER OUTPUT CODES (HEX) After a key is detected as being down, the keyboard encoder places a byte on its data bus which represents only the de- pressed key. The codes for some of the keys depend on the state of the "modifier"...
Page 197 Page 3.13 ENCODER OUTPUT CODES (HEX) Shifted Control Control Caps Lock Down Shifted (Yes/No) Shift Code Code...
Page 198 Page 3.14 ENCODER OUTPUT CODES (HEX) Down Shifted Control Caps Lock Control Code Code Shift (Yes/No) Shifted BACK SPACE LINE FEED RETURN...
Page 199 Page 3.15 ENCODER OUTPUT CODES (HEX) Caps Lock Down Control Control Shifted Code Shift (Yes/No) Code Shifted SPACE...
Page 200 Page 3.16 ENCODER OUTPUT CODES (HEX) Shifted Control Control Caps Lock Down (Yes/No) Code Shifted Shift Code DELETE ENTER HELP...
Page 201 Page 3.17 ENCODER OUTPUT CODES (HEX) Control Control Caps Lock Down Shifted (Ves/No) Shifted Code Code Shift D CHR ICHR D LINE I LINE (up arrow) (down arrow) (right arrow) (left arrow) HOME BREAK -(keypad) .(keypad) 0 (keypad) 1(keypad) 2 (keypad) 3 (keypad) 4 (keypad) 5 (keypad)
Page 202 Page 3.18 ENCODER OUTPUT CODES (HEX) Caps Lock Down Control Shifted Control Code Code Shift (Yes/No) Shifted 7 (keypad) 8 (keypad) 9 (keypad) FAST REPEAT CAPS LOCK SHIFT (right) CTRL SHIFT (left) (NC) (NC) RESET Resets Resets Computer Computer...
Page 203: Keyboard Key Layout
Page 3.19 KEYBOARD KEY LAYOUT Pictorial 3-2 shows the key layout of the keyboard. 0 CHR OEL LINE HOME RESET I CHR INS LINE SELT TE HELP CRPS CTRL Q, Q Q z Qx c PICTORIAL 3-2 Keyboard Layout...
Page 204: Chapter 4 Video Logic Board Description
Page 4.1 Video Logic Board Description User Options and Jumpers Theory of Operation Programming Data . 4.29 Circuit Description 4.48 4.69 Troubleshooting Replacement Parts List 4.70 Semiconductor Identification 4.72 4.106 Circuit Board X-Ray View Interconnect Pin Definitions 4.107 Schematic .. (Inside Envelope at rear of manual)
Page 205: Description
DESCRIPTION The video logic board produces video signals for an internal (in the All-In-One model) or external (Low-Profile model) video monitor. (An external monitor is also used with the All-In-One model for color displays.) Signals available include composite monochrome video, com- posite sync, horizontal sync, vertical sync, and three planes of noncomposite video for use with RGB type color monitors.
Page 206 THIS PART MAY NOT BE IN ALL UNITS. C ON T R A S T BLACK LEy - '':-Ieg '--, t. * CREEN 1 4 B L1 E e& '+ 3~,0& I ). ~+ J 8' r "Iitr' i IIIIMit ~II+ -' "' ——...
Page 207 INSET CHARACTER 01234567 CHARACTER SCA N LINE LINES HCR IZONTAL SCAN I. INES PICTORIAL 4-2 Video Display...
Page 208: User Options And Jumpers
Page 4.3 USER OPTIONS AND JUMPERS Refer to Pictorial 4-1 as you read the following information. Circuit Board Jumpers The video logic circuit board jumpers perform the following functions: J301 — S e l ects the polarity of the vertical sync signal for the internal monitor.
Page 209: Contrast Control
Page 4.4 USER OPTIONS AND JUMPERS J307 — T h i s jumper allows for different types of RAM to be used. 1. If the jumper is placed on the side marked "LOW 32K", lower 32K type RAM chips are selected.
Page 210: Theory Of Operation
Page 4.5 THEORY OF OPERATION General Theory The video logic board signals produce 25 lines of characters on the display screen with 80 characters per line. The board also controls the display colors or gray scales, depending on whether a color or monochrome display is used, and it con- tains the light pen circuitry.
Page 211: Theory Of Operation
THEORY OF OPERATION After a keyboard key is pressed ("7", for example) and soft- ware determines that it is time to display the character, the main microprocessor obtains the nine bytes of data that define the character's shape from the "7" entry in the font table and places these nine data bytes in proper locations in video mem- ory.
Page 212 page 4.7 THEORY OF OPERATION If you only want monochrome, you need only one of the three memory planes. Green is used because the green gun is set for greatest intensity for proper color displays. If a monochrome display is used with the three memory planes, eight levels of intensity (brightness) can be produced, which corresponds to the above colors.
Page 213 Page 4.8 THEORY OF OPERATION Detailed Theory When software determines that it is time to display a charac- ter, the main processor (8088) obtains nine bytes of data that define the character's shape from the font table and places the bytes in proper locations in video memory (VRAM). Then, when the display scan lines are refreshed by reading out of video memory, the character will be properly displayed on the screen.
Page 214 IN SET 1 CHARACTER 0 0 0 0 0 0 0 0 0 1234567 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 SCAN 9 DATA 0 0 0 0 0 1 0 0 LINES 3 0 0 0 0 1 0 0 0 BYTES IN...
Page 215 BLUE S H IFT GREEN E G I STER 64K OR BLUE 32K x 8 SHIFT GREEN MICRO- REGISTER SHIFT PROCESSOR REGISTER 16- BIT COUNTER 12- B IT 4- B IT COUNTER COUNTER CRT-C PICTORIAL 4-4 Add Memory And Counters...
Page 216 Page 4.9 THEORY OF OPERATION Then the CRT-C selects these same 80 characters again and again, as the 4-bit scan line counter selects one scan line after another until all nine scan lines of the first character row are displayed. Then the 4-bit scan line counter starts over and the 11-bit character counter selects the next character row in memory.
Page 217 page 4.10 THEORY OF OPERATION Conversion From Character-Based To Pixel-Based Display Refer to Pictorial 4-4 (Fold-out from Page 4.8). If we combine the 4-bit scan line address with the 12-bit video refresh ad- dress, then a 16-bit address is produced as shown. Also, if we increase the RAM size to 32 kilobytes, we have enough memory to store not only every character (80 x 25 = 2000...
Page 218 Page 4.11 THEORY OF OPERATION Actual Theory The following paragraphs describe the actual video operation of the Z-100 family of Computers. As shown in Pictorial 4-5, the video logic board consists of: A CRT controller. A video RAM mapping module. Three video RAM planes (arrays).
Page 219 Page 4.12 THEORY OF OPERATION CRT-C (CRT Controller) The screen is updated 60 times per second (when set for 60 Hz), with data (characters) from video RAM. During a sweep of the display beam, the CRT-C generates video RAM address VRAMA2 (see Pictorial 4-5) and reads a byte repre- senting eight pixels.
Page 220 5 H I FT BLUE» Q ~R EGISTER GREEN~» BLUE V I DEO 5 H IF T GREEN RE G II STER SHIFT VRAMA FIVRAMA) 32K or 64K REGISTER VIDEO RAIVI MA PP I NG MODULE VIDEO 5 I GNALS (Data to he VRAMA8 8808 pP...
Page 221 NOTES: 1. The boundry between the displayed and the non-displayed areas CPU ADDRESS SPACE (HEX) varies in address depending on the screen mode (9 lines per character, 16 line graphics, etc. ). I n a s y s tem with 32K RAM's installed, areas 'A' a n d ' B ' LINE 0 wrap back into the displayed 32K space.
Page 222 Page 4.13 THEORY OF OPERATION Once all the scan lines for the character line have been sequ- enced through, the base address for the memory refresh ad- dress (MA11-MAO) is advanced to the first character of the next line. This process is repeated until all lines have been displayed on the screen, at which time vertical retrace takes p lace.
Page 223 Page 4.14 THEORY OF OPERATION In general (assuming the start address is 0), the address of byte "c", scan line "s", and row "r" would be: r x 80 + c x 16 + s O~ r — 24 I'OW I, s canline s, 0 ~ s ~ 8 c haracter c, 0 ~ c ~ 7 9...
Page 224 Page 4.15 THEORY OF OPERATION Actual Theory Video RAM Mapping Module As shown in Pictorial 4-2, the rows are numbered 0 through 24 and the characters, or columns, are numbered 0 through TOTAL D I S PLAYED 79. The 225 horizontal scan lines are numbered 0 through SCAN SCAN 224, and the 640 columns of pixels are numbered 0 through...
Page 225 Page 4.16 THEORY OF OPERATION Notice that there are "holes" in the addressing map. These holes correspond to the characters 80 - 127 of each row. Since these are illegal character numbers for each row and will not be displayed, you should avoid these addresses. Using them may inadvertantly modify pixels of VRAM which you do not intend to modify.
Page 226 LOGICAL SCREEN ADDRESS 11 10 MA PP ING BASE ADDRESS 8 8 IT ADDER CRT-C [0,127j x • HORIZONTAL BYTE INDEX y- VERTICAL BYTE INDEX D 511 PICTORIAL 4-9 Video RAM Mapping Module...
Page 227 Page 4.17 THEORY OF OPERATION Remembering that X is less than 80, you see that the high address byte does not "sequence" nicely. As sequential hori- zontal byte addresses are generated for each scan line, the values being generated for the high byte of the address (be- fore they enter the mapping ROM) are: ROM(A) 0 0 0 0...
Page 228 Page 4.18 THEORY OF OPERATlON Severa! mapping samples are shown below. index) Y (row X (column index) VRAMA1 address F(VRAMA1) O OO O H OOOOH 0010H 0001H 00 02 H 0020H 0 0 0 0 1 1 1 04FOH 004 FH 0001H 0080 H 008 1H...
Page 229 Page 4.19 THEORY OF OPERATlON The full address generated out of the mapping ROM reor- ganizes the conventional notation into the desired CRT-C ad- dress. The 8-bit adder is used in scrolling the screen by ad- vancing the start address. Once the start address is advanced, the data representing the line on the screen is in a different physical address.
Page 230 Page 4.20 THEORY OF OPERATION By translating the physical address, it is possible to move the mapping function along so that it operates on consecutive "lines" of RAM. The use of this adder is analagous to that of a magnifying glass. The magnifying glass makes a small portion of text easier to read by enlarging the print.
Page 231 Page 4.21 THEORY OF OPERATION This means that the value of the byte to turn on the following "x" marked pixel would be one. 0000000X Similarily, 85 (55 hex) would turn on the following pixels: OXOXOXOX To display the pixel in the upper left-hand corner of the screen, 128 (80 hex) would be stored in address 0 of video RAM.
Page 232: Video Ram
Page 4.22 THEORY OF OPERATION Video RAM Each of the three video planes reside in a distinct 8088 64K byte segment. The green plane is at address EOOOOH, the red plane is at address DOOOOH, and the blue plane is at address COOOOH.
Page 233 page 4.23 THEORY OF OPERATION Another bit totally disengages all planes of video RAM from the CPU. When disengaged, the CPU can neither write to nor read from VRAM. This makes sure that VRAM does not conflict with the boot ROM. Note that though the RAM may be disengaged from the CPU, any enabled planes will be dis- played on the monitor.
Page 234 Page 4.24 THEORY OF OPERATION There are two other bits that control screen functions. These two bits may be used to clear the screen without explicitly modifying each byte of the plane with a memory modification generated by the 8088. These bits do not work in conjunction with the write bits and, in fact, override them.
Page 235 Page 4.25 THEORY OF OPERATION Technical Description Most light pens, in addition to providing a pulse from a detec- tor, also provide a switch. U134-B (LS14, pins 3 8 4, located on the main circuit board) buffers the switch input and feeds it to U114 pin 8 (PA6 —...
Page 236 Page 4.26 THEORY OF OPERATION The LTPNSTB signal is applied to video logic board U362 pin 12, the D input of a 74ALS74 flip-flop. This is synchronized by video clock signals and the final output is taken from U356 pin 9 (the Q output of the flip-flop). The signal is then applied to U330 pin 3 (CRT-C —...
Page 237 Page 4.27 THEORY OF OPERATION & low bytes (R12 & R13), and subtract the latter from the former. CHA R A C T E R POSITION LIGHT PEN ADDRESS + START ADDR For example, if you get 01EDH for the LIGHT PEN and 0140H for the START ADDRESSES, then: Character position 01EDH...
Page 238 Page 4.28 THEORY OF OPERATION Recall that the 16-bit memory value for VRAM is organized as follows: DT D6 11 10 CHARACTER NUMBER W ITH IN A G I YEN ROW SCAN LINE NUMBER ROW NUMBER In this example, CHAR ¹ SCAN LINE ¹...
Page 239: Programming Data
page 4.29 PROGRA M M ING DATA Port Addresses The information in this section concerns the video logic circuit board only and is for the experienced programmer. Program- ming information for the entire system is contained in "Program- ming Data" toward the end of this Manual. The following chart lists the port addresses for devices that are located on the video logic circuit board.
Page 240 Page 4.30 PROGRA M M ING DATA Modifying the Video Control Register NOTE: It is assumed that the CRT-C (68A45) and the CRT I/O control port (68A21) have been correctly initialized. The I/O port address for this control port is D8 hex. The upper four bits (D7 —...
Page 241 Page 4.31 PROGRA M M ING DATA The memory map of the three planes is as follows. Addresses are in hex. OEFFFF Green: OEOOOO 6 4 K Red: O DOOOO ODFFFF OCFFFF Blue: O C OOOO DO 0 — Enables red plane 1 —...
Page 242 Page 4.32 PROGRA M M ING DATA The next three bits control "simultaneous write" capability. D6 0 — When data is written into any color (R, G, or B VRAM), the same data is also written into blue VRAM. 1 — Data can be written into blue VRAM only if the blue plane is accessed.
Page 243 Page 4.33 PROGRA M M ING DATA — The screen is blanked (black). — All planes are enabled. VRAM data appears. — Blue and green planes are enabled. VRAM data appears. — Blue and red planes are enabled. VRAM data ap- pears.
Page 244 Page 4.34 PROGRA M M ING DATA The following are examples of how the screen can be controlled by data bits D3-DO. Exam le1: FLASH B L U G R N RED — D3 is 0, so the flash bit is t urned on a n d V R A M data is masked.
Page 245 Page 4.35 PROGRA M M ING DATA Actual VRAM data will appear on the screen with the green plane disabled. "Green plane disabled" means that there will be no green pixel turned on. The actual data contained in the green plane's VRAM (OEOOOO — OEFFFF) is unaff ected. The normal operating mode is as follows.
Page 246 Page 4.36 PROGRA M M ING DATA In a similar manner, D5 controls green and 04 controls red VRAM. ~ Exam le 1: VRAM ENABLE BL U GRN 0, so VRAM is enabled. D6 = 1 , s o W RITE BLU is off . 0, so 058 D4 WRITE GRN and...
Page 247 Page 4.37 PROGRA M M ING DATA Exam le 2: Assume that all three planes of VRAM have been cleared (00). Then suppose we want to write OFF (hex) (a solid line ) on the screen to location 0000 in magenta (red and blue).
Page 248 Page 4.38 PROGRA M M ING DATA Typically, all three planes would be displayed. So the I/O port would read: port D8 (hex) 08 (hex) -- alphanumeric mode. = = ) For some graphic applications, where you do not want to write to more than one plane at a time, the value would be ) 78(hex.) port D8 (hex)
Page 249 Page 4.39 PROGRA M M ING DATA Modifying the CRT-C Register The CRT-C {CRT Controller) has an address register AR [port address DC (hex)] and registers RO-R17 [port address DD (hex)]. The Address register is a pointer register. It points to one of the 18 registers RO-R17.
Page 250 Page 4.40 PROGRA M M ING DATA Under normal operating conditions, this will be the case. When in doubt, you should initialize the latch to meet these conditions. Example: MOV AL, 00CH LOAD OUT ODCH, AL START ADDRESS A L , ODDH HIGH BYTE MOV AH, AL IN AH...
Page 251 page 4.41 PROGRA M M ING DATA The screen is organized as 640 (decimal) pixels [or 80 (deci- mal) bytes] horizontally across the screen. To the CPU (or system logical address space), the top left-most byte is always at 0000. (These definitions apply to all planes.) The byte ad- dresses increase from left to right on any given scan line.
Page 252 Page 4.42 PROGRA M M ING DATA At the right-hand side of the screen, past the 80th location, there are "holes" in the logical address space. [See Pictorial 4-2, fold-out from Page 4.2.] You must not attempt to use these-locations, especially while 32K RAMs are used. For ex- ample: never try to write to location OE0150 (hex) —...
Page 253 Page 4.43 PROGRA M M ING DATA ~ Exam le1: The CRT-C has been programmed for nine scan lines per character row, the CPU writes FO (hex) to location OC693F (hex), and OC (hex) points to the blue plane. Problem: Figure out the location of 693F (hex) and what is displayed there.
Page 254 Page 4.44 PROGRA M M ING DATA Therefore, the VRAM location is ODS(hex) + 24(hex) 6C24(hex) = = ) 9 bits 7 bits Exam le3: Problem: Where on the screen is location 35E3 (hex)? Divide 35E3 (hex) into its X and Y coordinates. >06B(hex) + 63(hex) 35E3(hex) The X coordinate 63 (hex) falls into the "hole"...
Page 255 Page 4.45 PROGRA M M ING DATA Clearing the Screen The "clear screen" feature allows you to initialize all the view- able VRAM locations to either 00 (hex) or FF (hex). The CRT I/O control port (68A21) has two control ports, A and B.
Page 256 Page 4.46 PROGRA M M ING DATA Exam let: Clear the screen. Re a d port D8 (hex) and save the status. Ini t ialize CRT control port D8 (hex) to OF (hex). This will instantaneously blank the screen, since all three planes are disabled.
Page 257 Page 4.47 PROGRA M M ING DATA ~ Exam le2: Set the screen. Re a d port D8 (hex) and save the status. T u r n o n the FLASH bit and those planes which were originally enabled. AL , ODSH AND AL,OF7H OUT ODSH,AL This will instantaneously set the color of the screen to...
Page 258: Circuit Description
Page 4.48 CIRCUIT DESCRIPTION Video Logic Circuit Board Video Processing Circuits Cathode Ray Tube Controller (CRT-C) The CRT-C, U330, fetches the characters to be displayed and provides horizontal and vertical timing. It also keeps track of the affected character if the light-pen circuits are used. Briefly, here's what each line does.
Page 259 Page 4.49 CIRCUIT DESCRIPTION MAO-MA11 Me mory address lines. Point to the current character line, and the character in that line. RAO-RA3 Row address lines. Points to the current scan line in the current character line. Writing to a CRT-C Register To select a specific CRT-C register (RO-R17), the CPU must first program the address register (AR).
Page 260 Page 4.50 CIRCUIT DESCRIPTION How the CRT-C Addresses RAM As mentioned before, the CRT-C is normally programmed to emulate the H19 video terminal. That is, the display will con- tain 25 lines, 80 characters per line, and nine scan lines (rows) per character line.
Page 261 Page 4.51 CIRCUIT DESCRIPTION When line VIDRAMSEL is low, the multiplexers pass the CRT-C address bus to the VRAM address bus. RAO-RA11 is the lower 4 bits, DAO-DA3; and MAO-MA11 are bits DA4- DA15. This causes the address line to increment by 16 for every scanned character.
Page 262 Page 4.52 CIRCUIT DESCRIPTION Lines DAO-DA15 connect to address multiplexer U360 and U373. This circuit splits the address for RAS and CAS timing. RAS timing occurs when ADMUX is high, coupling the follow- ing lines to the outputs: VA7 VA6 VA5 VA4 VA3 VA2 VA1 VAO DA9 DA8 DA7 DA6 DA5 DA4 DA1 DA2 CAS timing occurs when ADMUX goes low, causing: V A7 V A 6...
Page 263 page 4.53 CIRCUIT DESCRIPTION Converting RAM Data to Video There are two sets of data lines at the video memory. One is an 8-bit bus, BDO-BD7, used by the CPU to write to RAM; and three 8-bit output buses, one for each color. The output buses go to the CPU through U339, U310, and U316.
Page 264 Page 4.54 CIRCUIT DESCRIPTION When they are asserted, the enable lines from the PIA (U345) gate their respective dot video color to the outputs at pins 14, 15, and 16. When the FLASH line — also from the PIA — is asserted, the output lines selected by the enable lines will go high, saturat- ing that color onto the screen and masking any video data on that line.
Page 265 Page 4.55 CIRCUIT DESCRIPTION Video Output Color Output The 3 RGB lines from U329 connect to U307. This buffer provides red, green, and blue video pulses to P303. Logic 1 equals color on; 0 is black level. The horizontal and vertical sync pulses connect to U320, pins 12 and 9.
Page 266 Page 4.56 CIRCUIT DESCRIPTION If none of the RGB lines were asserted U309 pin 2 would go high to place U322 pin 6 at logic zero. This lowers Q301's emitter voltage to the black level. Composite sync from U355 pin 11 provides horizontal and vertical sync pulses at the blacker-than-black level.
Page 267 Page 4.57 CIRCUIT DESCRIPTION CPU-Video Communications Overview The CPU can communicate with the video board through sev- eral I/O ports, or by read/writing the video RAM. It uses the I/O ports to access the CRT-C, the PIA, and the light pen circuits.
Page 268 Page 4.58 CIRCUIT DESCRIPTION A nother video I/O c i rcuit is th e PI A a t U 3 45 . T his i s u s e d for address decoding, controlling the display, and performing some VRAM operations. The CPU selects the PIA at ECLK time (pin 25) by asserting CRTIOCS at pin 23.
Page 269 Page 4.69 CIRCUIT DESCRIPTION Memory Select Circuits The memory select circuits are centered around U371, VRAM- SEL, a 256 x 4 PROM. This IC is used when the CPU wants to access the red, green, or blue memory banks. VRAMSEL is selected when CRTRAM ENABLE is asserted at the PIA.
Page 270 Page 4.60 CIRCUIT DESCRIPTION Video logic boards can have either 32K or 64K parts installed. Current software, however, requires only 32K parts. CRTRAMSEL asserts whenever pin 11, 10, or 9 asserts. This connects to U372 pin 12 in the lower left corner of the schema- tic.
Page 271 Page 4.61 CIRCUIT DESCRIPTION Read Data Buffers The CPU reads the addressed data through either U339, U310, or U316. When the CPU reads VRAM, the memory places data on the inputs of these latches. To read a particular bank, the CPU asserts RSEL, GSEL, or BSEL. For example, to read the data in the green video memory bank, the CPU addresses the desired video memory section (to be explained shortly) and asserts GSEL at U371 pin 10.
Page 272 Page 4.62 CIRCUIT DESCRIPTION Video RAM Overview The video RAMs ar e 32 K o r 6 4 K x 1-b i t d y n amic RA Ms . The RAMs are arranged into three banks, 64K apart; one bank for each of the primary colors.
Page 273 page 4.63 CIRCUIT DESCRIPTION CRT-C Read The CRT-C reads all three banks at the same time; the enable lines at U337 select which banks are to be displayed as explained previously. When the CRT-C has control, VIDRAM- SEL is low and couples to pins 13, 5, and 11 of U350. This forces pins 12, 6, and 8 of U350 to logic 1.
Page 274 Page 4.64 CIRCUIT DESCRIPTION CRT-C CRT-C ADMUX VID STROBE CPU STROBE CCK1 LOAD S.R. CCK2 Pictorial 4-12 Video Board Timing...
Page 275 Page 4.65 CIRCUIT DESCRIPTION Timing and Video Arbitration Timing Refer to the Schematic Diagram and Pictorial 4-12 as you read the following materials. The 14.112 MHz crystal-controlled oscillator at U368 provides the basic timing for the video circuits. This signal couples through U344 pin 11 to provide dot clock and couples through U344 pin 6 for inverted dot clock.
Page 276 Page 4.66 CIRCUIT DESCRIPTION The third RAS cycle of the video timing cycle is reserved for the CPU. If the CPU doesn't attempt to read or write memory, RAS will not assert during the time marked "CPU." If the CPU does attempt to read or write memory RAS will assert and the memory access can take place.
Page 277 Page 4.67 CIRCUIT DESCRIPTION CRTRAMSEL also goes to U379 pin 11 to set up the bus arbitration circuits for a read/write request from the CPU. If the operation is a CPU write, then U379 pin 3 goes high. If the operation is a CPU read, then MEMR is clocked into *SYNC asserts.
Page 278 Page 4.68 CIRCUIT DESCRIPTION At the same time, U361 pin 8 goes low to bring VIDRAMRDY high. The CPU leaves the wait state and finishes processing the instruction. CRTRAMSEL goes high to drive U379 pin 13 low. Since VIDRAMSEL is also low, U355 pin 3 goes to logic zero to clear U361.
Page 279 Page 4.69 7ROUBLESHOO7ING Use the following chart for help in identifying the source of problems. The chart lists conditions and possible causes for specific problems. If you cannot resolve the problem, refer to the warranty and service information supplied with your Computer.
Page 280: Parts List
Page 4.70 REPLACEMENT PARTS LIST Circuit Board Video Logic Description C IRCUIT H E A T H Comp. No. Part No. Resistors All resistors are 1/4-watt, 5%, unless specified otherwise R301 10-1204 1000 I I control (may not be in all units) RP301 9-99 1000 tt resistor pack...
Page 281 page 4.71 REPLACEMENT PARTS LIST CIRCUIT HEATH DESCRI P T ION Comp. No. Pa r t No. Capacitors 180 pF ceramic C301-C302 21-746 .1 p.F ceramic 21-762 C303 25-820 10 pF electrolytic C304 C305-C307 21-762 .1 rr.F ceramic 10 p.F electrolytic 25-820 C308 21-762...
Page 282: Semiconductor Indentification
Page 4.72 SEMICONDUCTOR IDENTIFICATION Component Number Index This section is divided into four parts. The "Component Number Index" relates circuit component numbers to Heath Part Numbers. The "Part Number Index" relates part numbers to manufacturers' part numbers, as well as providing lead con- figuration drawings for each part.
Page 283 Page 4.73 SEMICONDUCTOR IDENTIFICATION CIRCUIT HEATH COMPONENT PART NUMBER NUMBER 443-983 U336 443-115 U337 443-1058 U338 443-837 U339 U340 443-1 106 443-1 1 06 U341 443-1 106 U342 443-983 U343 U344 443-915 U345 443-1014 444-133 U346 443-1106 U347 443-1 106 U348 443-1 106 U349...
Page 284 Page 4.74 SEMICONDUCTOR IDENTIFICATION Part Number Index This index shows a lead configuration detail (basing diagram) of each semicoductor part number. Transistors HEATH MAY BE DESCRIPTION LEAD PART REPLACED CONFIGURATION NUMBER WITH 417-118 2N3393 Integrated Circuits HEATH MAY BE DESCRIPTION LEAD PART REPLACED...
Page 285 page 4.75 SEMICONDUCTOR IDENTIFICATION Integrated Circuits (cont'd) HEATH MAY BE DESCRIPTION LEAD PART REPLACED CONFIGURATION NUMBER WITH v cc 443-797 74LS10 Triple 3-input NAND GN D INPUTS INPUTS OUTPUT OUTPUT Vcc ' STROBE 4A 443-799 74LS157 Quad 2-line-to-1-line Multipliers SELECT OUTPUT OUTPUT INPUTS...
Page 286 page 4.76 SEMICONDUCTOR IDENTIFICATION Integrated Circuits (cont'd) MAY BE DESCRIPTION LEAD HEATH PART REPLACED CONFIGURATION NUMBER WITH V cc 8 0 CLO C K CLEAR CLEAR CLEAR CLEAR Octal D flip-flop 443-805 74LS273 CLEAR CLEAR C LEAR C LE A R CLEAR 10 2 Q 3 0 ENABLE...
Page 287 Page 4.77 SEMICONDUCTOR IDENTIFICATION Integrated Circuits (cont'd) HEATH MAY BE LEAD DESCRIPTION PART REPLACED CONFIGURATION NUMBER WITH 443-875 74LS32 Quad 2 i nput OR V cc CL OC K D CK CLEAR CLEAR CLEAR 443-879 74LS174 Hex D flip-flop CLEAR CLEAR I Q G ND 443-891...
Page 288 Page 4.78 SEMICONDUCTOR IDENTIFICATION Integrated Circuits (cont'd) HEATH DESCRIPTION MAY BE LEAD PART REPLACED CONFIGURATION NUMBER WITH 443-915 Quad 2-input 74S86 Exclusive-OR (IIU D 443-967 Hex inverter 7406 G ND CLOCK Quad D flip-flop 443-983 74S175 CK CL CILAR I O 3 2 3 1 3 0 2 9 28 2 7 2 6 2 5 Z 4 2 3 2 2 Z l 4 0 39 38 3 7 3 6 3 5 3 4 3 3...
Page 289 Page 4.79 SEMICONDUCTOR IDENTIFICATION Integrated Circuits (cont'd) HEATH MAY BE DESCRIPTION LEAD PART REPLACED CONFIGURATION NUMBER WITH © — c a c c : cc : l a 4 0 39 38 37 36 35 34 33 3 Z 3 1 30 Z 9 Z B Z7 Z 6 Z 5 2 4 2 3 2 2 Z I 443-101 4 68A 21...
Page 290 Page 4.80 SEMICONDUCTOR IDENTIFICATION Integrated Circuits (cont'd) HEATH MAY BE DESCRIPTION LEAD REPLACED PART CONFIGURATION NUMBER WITH CL OCK V):9 " C K CK 0 CI LAR CLEAR Hex D flip-flop 443-1053 74S174 LI Ak CI EAR CLEAR 1 0 G ND OUTPUTS RIPPLE...
Page 291 WITH C A S 443-1106 MCM66330 RAM32k x 1 MCM6665 RAM64K x1 443-970 Available only C S2 C S I from Zenith '. I Data Systems 444-102 Video memory decoder or Heath Company Available only from Zenith 444-103 Video I/O decoder...
Page 292 MAY BE HEATH CONFIGURATION PART REPLACED WITH NUMBER E I P/E2 E3 CC NC 2 4 2 3 Available only PROM from Zenith 444-127 Data Systems PROM 256x 8 or Heath Company 18S22 2<l Available only from Zenith 444-133 Data Systems...
Page 293 page 4.83 SEMICONDUCTOR IDENTIFICATION PAL Equations 444-114/Video Ram Controller Q10 ~ co V I DRAM SEL Q15 ~ V ID STR B a A D M UX ~ CAS F RAS Q40 oo GND 8 LOGIC EQUATIONS * Q55 + Q0 5 *Q30 + QO *Q60 + Q25 *Q70*VIDRAMSEL Q40 * Q65 + Q 1 5 *Q40 + Q7 0 *Q10 + QO *Q30*VIDRAMSEL ADMUX Q30 + Q6 0 * Q05 + Q3 5 *Q60*VIDRAMSEL...
Page 294 page 4.84 SEMICONDUCTOR IDENTIFICATION 444-115Nideo Attribute Controller ~ VCC ENBLR ENBLG ENBLB FLASH BOUT DISEN u ~ GOUT CURSOR ROUT RIN ~ GND o LOGIC EQUATIONS *CURSOR *RIN ROUT *FLASH + D ISEN DISEN *ENBLR *ENBLR *CURSOR + DISEN *ENBLR *RIN *FLASH + D ISEN *CURSOR */GIN...
Page 295 Page 4.85 SEMICONDUCTOR IDENTIFICATION 444-133/CLRSCRN Data Buffer for Video RAM with Clear Screen and Set Screen Functions CLRSCRN OUTO OUT1 OUT2 OUT3 IN3 v OUT4 F OUT5 OUT6 IN6 c o O U T 7 GND 8 LOGIC EQUATIONS CLRSCRN * INO + CLRSCRN * SET OUTO CLRSCRN * IN1 + CLRSCRN * SET OUT1...
Page 296 page 4.86 SEMICONDUCTOR IDENTIFICATION ROM Codes t i t l e VRAMSEL video ram select prom for the Z-100 ZDS part n o . : 444-102 r el e as e d a t e : 5/21/ 82 prom: 82s129 (256x4) checksum: Oeef...
Page 297 Page 4.87 SEMICONDUCTOR IDENTIFICATION VRAMSEL video r am select prom for the Z-100 0020 0021 OO22' 0023' 0024' 0025 O026' 0027' 0028' 0029' 002A' 002B' Of}1 002C' 002D 002E' 002F 0030' 0031' 0032' 0033' 0034' 0035 0036 0037' 0038 0039 003A 003Br 003C'...
Page 298 page 4.88 SEMICONDUCTOR IDENTIFICATION VRAMSEL video ram select prom for the Z-100 004E' 004F' 0050' 0051' 0052' 0053' 0054' 0055' 0056' Oi h 0057' 0058' 0059' 005A' 005B' 005C' 005D' 005E' 005F' 0060' 0061 0062 ' 0063' 0064' 0065' 0066' Of}1 0067' 0068'...
Page 299 page 4.89 SEMICONDUCTOR IDENTIFICATION VRAMSEL video ram select prom for the Z-100 007C' 007D 007E' 0 f 11 007F' 0080' Of h 0081' 0082' 0083 QQ84' Ofjl 0085' 0086' Of h 0087 0088' Of 11 0089 008A' 008B' 008C' Of h 008D' QQ8E' 008F'...
Page 300 page 4.90 SEMICONDUCTOR IDENTIFICATION VRAMSEL video ram select prom for the Z-100 OOAA' Of'h OOAB' QQAC' 0 f'h OOAD' OOAE' OOAF' QOBQ' 0 f'h OOB1 0 f'h OOB2 0 f'h OOB3 0 f'h OOB5' OOB6 OOB7' OOB9 OOBA Of h OOBB' 0 f'h OOBC'...
Page 301 page 4.91 SEMICONDUCTOR IDENTIFICATION VRAMBEL video ram select prom for the Z-100 nf}1 OOD8' OOD9' nona' OODB' OODC QODD' QQDE' OODF' nOVO' 0 f }1 OOE1 OOE2' OOE3' nf}l OOE5' QQE6' nf }1 QQE7' OOE8' QOE9' 0 f'h OOEA OOEB 0 f'h QQEC' OOED'...
Page 302 page 4.92 SEMICONDUCTOR IDENTIFICATION VRAMSEL video ram select prom for the Z-100 Macros: Symbols: B LU EN 0 0 0 6 GRN E N O OOA RED E N O O O O N o F a t a l e r r o r ( s )
Page 303 Page 4.93 SEMICONDUCTOR IDENTIFICATION — video i/o select prom t i t l e VIOSEL ZDS part n o . : 444-103 r el e ase d a t e : 5/21/82 82s129 prom: checksum: Oeba 0000 cseg se16821 e qu 0101b 0005 0006...
Page 304 page 4.94 SEMICONDUCTOR IDENTIFICATION VIOSEL- video i/o select prom 0020' 00fh 0021' 00fh 0022' Oofh 0023' Oofh 0024' 00fh 0025' Oofh 0026' 00fh 0027 00fh 0028' Oofh 0029' Oofh 002A' Oofh 002B Oofh 002C' Oofh 002D' Oofh 002E 00fh 002F' 00fh 0030' Oofh...
Page 305 page 4.95 SEMICONDUCTOR IDENTIFICATION VIOSEL video i/o select prom 004E' oofh 004F 00fh oofh 0050' oofh 0051' 00fh 0052 0053' 00fh 0054' oofh oofh 0055' oofh 0056' 0057' OOfh 0058' Oofh oofh 0059' oofh 005A 005B' oofh 005C' 00fh oofh 005D' 005E' OOfh...
Page 306 page 4.96 SEMICONDUCTOR IDENTIFICATION VIOSEL — video i/o select prom 00fh 007C 00fh 00?D OOfh 007E 00fh 007F' Oofh 0080' 00fh 0081' 0082' 00fh 00fh 0083' oofh 0084' Oofh 0085' oofh 0086' OOfh 0087' Oofh 0088' Oofh 0089 Oofh oofh 008B' Oofh 008C...
Page 307 page 4.97 SEMICONDUCTOR IDENTIFICATION VIQSEL — video i/o select prom Oofh OOAA' OOAB' 00fh 00fh OOAC' 00i'h OOAD' 00fh OOAE' 00fh OOAF' 00fh OOBO' 00fh OOB1 ' OOB2 ' Oofh 00fh OOB3' OOB4' Oofh oofh OOB5' 00fh OOB6' Oofh OOB7' OOB8' 00fh OOB9'...
Page 308 page 4.98 SEMICONDUCTOR IDENTIFICATION VIOSEL video i/o select prom OOD8 ' se16821 OOD9 ' se16821 OODA' se16821 OODB' se16821 OODC' se16845 OODD' se16845 OODE' l i g h t p e n OODF' Oofh OOEO' Oofh OOE1 ' Oofh Oofh OOE2 OOE3' 00fh...
Page 309 page 4.99 SEMICONDUCTOR IDENTIFICATION VIOSEL — video i/o select prom Macr os: Symbols: L IGHTP 0 0 0 3 SEL 6 8 2 00 05 SEL 684 00 06 N o F a t a l e r r o r ( s )
Page 310 page 4.100 SEMICONDUCTOR IDENTIFICATION t i t l e VRMM Video Ram Mapping Module cseg . radi x Z DS part n u mber . : 4 4 4 - 1 2 7 release date: 5/21/82 prom: TBP18s22 ( 2 56 "8) c hecksum: 7 f 8 0...
Page 311 page 4.101 SEMICONDUCTOR IDENTIFICATION...
Page 312 Page 4.102 SEMICONDUCTOR IDENTIFICATION 5F r 6F ' 71 r...
Page 313 page 4.103 SEMICONDUCTOR IDENTIFICATION...
Page 314 page 4.104 SEMICONDUCTOR IDENTIFICATION...
Page 315 Page 4.105 SEMICONDUCTOR IDENTIFICATION E9 f...
Page 316: Circuit Board X-Ray View
Page 4.106 CIRCUIT BOARD X-RAY VIEW NOTE: To find the PART NUMBER of a component for the pur- pose of ordering a replacement part: Fi n d the circuit component number (R303, C304, etc.) on the X-Ray View. I o c ate the same number in the "Circuit Component Number"...
Page 317 L381CONTRAST aaaf b b . 1 i . U38 1,::: =:.-: -:- XH8 ~, iR 8 1 C382- 28 Op'T-'-' - ' ' - * : : " " - " : " ' " — . ' - b b b b b @b ..U3 8 IT M PPED RGB - ;V322-...
Page 318 0 0 0 „"-7 ..6 f Cl Cl (Y) 2 )~ 3 8 0 0 0 0 '"14 I '4 " tI 4 8 4 2 • 1! 39 41 )GIC CIRCUIT BOARD m the component side. >wn in red, bottom side shown in gray.
Page 319: Interconnect Pin Definitions
Page 4.107 INTERCONNECT PIN DEFINITIONS The following statements briefly define the video logic circuit board connecting pins. BAO-BA23 Buffered address lines. BDIO-BDI7 Buffered data input lines. BDOO-BDO7 Buffered data output lines. BMWRT Buffered memory write signal. DB IN Control signal that requests data on the data input bus.
Page 320 Page 4.108 INTERCONNECT PIN DEFINITIONS RESET Reset signal that resets the Computer to its power-on status. STVAL®SYNC Stat u s valid signal ANDed with the sync signal. VIDRAMRDY Video RAM ready. Causes the CPU to wait if the CPU attempts to access video RAM while the CRT-C is addressing video RAM.
Page 321 Page 4.)Q9 INTERCONNECT PIN DEFINITIONS +5 volts through pullup resistor. + 5 volts through pullup resistor. + 5 volts through pullup resistor. + 5 volts through pullup resistor. HSYNC Horizontal sync signal. Row address stobe signal. RDOTA Red dot (pixel) data signals. Red video signals.
Page 323 Page 5. I Video Deflection Board Circuit Description Troubleshooting Recalibration Replacement Parts List .. Circuit Board X-Ray Views Schematic (Inside Envelope at rear of manual)
Page 324: Circuit Description
page 5.2 CIRCUIT DESCRIPTION The video deflection board is only used in the all-in-one models of the Z-100 family of computers. It converts TTL signals com- ing from the video logic board to the voltages necessary to drive the CRT. The board contains the vertical circuits, horizontal cir- cuits, video amplifier, and the high-voltage power supply.
Page 325 Page 5.3 CIRCUIT DESCRIPTION High Voltage Power Supply The flyback transformer, TX102, uses the signal coming from Q103 to generate the acceleration voltage for the CRT. This voltage is rectified before it leaves the transformer. The secon- dary of TX102 also develops focus, blanking, and bias voltages for the CRT through C121, CR106, and CR108.
Page 326: Troubleshooting
Page 5.4 TROUBLESHOOTING Use the following chart for help in identifying the source of prob- lems. The chart lists conditions and possible causes for specific problems. If you cannot resolve the problem, refer to the war- ranty and service information supplied with your Computer. If you have electronics service skill, you may wish to service some problems yourself.
Page 327 WA R NING '-';, HI GH VOLTAGE - ' " LECT ION YOKE kl ROAM MAGNET , T ' ~ ROT A T E CENTERING ;, / PICTORIAL 5-1 Calibration Control Locat...
Page 328 WARNING H I GH VOLTAGE W I DTH COIL O~ VIDEO FOCLIS DEFLECT ION BR IT'E BOARD VERT SIZE PICTORIAL 5-1 bration Control Locations...
Page 329: Recalibration
Page 5.5 RECALIBRATION Boot the demo disk supplied with your Computer and utilize the rectangle surrounding the menu for the following proce- dures. Refer to Pictorial 5-1 for the following steps. NOTE: In the following adjustments, the controls called for will be on the video deflection circuit board unless stated otherwise.
Page 330 Page 5.6 RECALI BRATION For these adjustments, if you have the color memory option, run the program you have just entered. If you do not have the color memory option, simply follow the instructions in the following steps. Adjust the rear panel control labeled J14 until the display is at a comfortable brightness level.
Page 331 Page 5.7 RECALI B RATION Locate the one area of the four edges of the display that is the least straight. Adjust the foam m agnet on the post that protrudes from the yoke at the position which is closest to this location until the display edge is as straight as possible.
Page 332: Parts List
page 5.8 REPLACEMENT PARTS LIST CIRCUIT HEATH Description Comp. No. Part No. Resistors All resistors are 1/4-watt, 5%, unless specified otherwise. 6-102-12 1000 Q R101 R103 6-102-12 1000 Q 6-223-12 R106 22 kQ 6-102-12 R107 1000 Q 6-472-12 R109 4700 Q, 2% R112 6-103 10 kQ, 1/2-watt, 2%...
Page 333 page 5.9 REPLACEMENT PARTS LIST Resistors (Cont'd.) R329 6-681-12 680 0 R331 6-279-12 2.7Q 5% RX333 234-282 220 failsafe R337 6-101-12 100 ft R402 1-50-2 820 0, 2-watt R403 6-102-12 1000 0 R404 6-102-12 1000 ft R406 6-470-12 47ft 10% R407 6-331 330, t /2-watt, 10%...
Page 334 Page 5.10 REPLACEMENT PARTS LIST CIRCUIT H E AT H Desc r i ption Comp. No. Part No. Inductors 234-259 Width coil L101 234-260 Unearity coil L102 Transformers Horizontal drive 234-261 TX101 TX102 234-262 Horizontal sweep Diodes CR102 57-27 CR104 234-264 CR106 234-263...
Page 335 Page 5.11 CIRCUIT BOARD X-RAY VIEWS NOTE: To find the PART NUMBER of a component for the purpose of ordering a replacement part: Fi n d the circuit component number (R303, C304, etc.) on the X-Ray View. Lo c a t e the same number in the "Circuit Component Number"...
Page 336 ' " " Wm4c&4'XW~ ~ g - % >w ~ ' 'wtlAk : eagan~ X333 R401 ~ C118 I C317 B I, 1 ORG < "" P 2::: « ,". ~1$4~~ wms Q; .I g@g~, += +„ . ~G'f : CX117 ~: i RN S .
Page 337 ( Oj. g „ N 3) ~ 'k I~ R<Oe + + eaoa c o II Q ' ))p Qx129~ CR O+ „ P"; Rqqy>" ".", VERI', HOR IZ. CX))9 CII9 p R313.~ u "a)O3 S+ ~ e3og~~~ c3or RI4$ Vf I H)SE g ": .
Page 338: Circuit Board X-Ray View
Page 6.1 Floppy Disk Controller Description User Options Programming Data Theory of Operation 6.21 Detailed Circuit Description 6.23 Troubleshooting 6.32 Calibration 6.34 Replacement Parts List . 6.38 Semiconductor Identification 6.39 Circuit Board X-Ray View 6.49 Interconnect Pin and Signal Definitions 6.50 Schematic ..
Page 339: Description
Page 6.2 DESCRIPTION The Floppy Disk Controller Card is located in the S-100 card cage in the back of the Z-100 Computer, where it operates as a slave unit on the bus. The Card has the following features: • A u s er-selectabte port address. •...
Page 340: User Options
Page 6.3 USER OPTIONS Card Clock Speed The Floppy Disk Controller Card is supplied already confi- gured to operate in a Z-100 Family Computer. If the Card will ever be used in a non-standard configuration, then the clock speed jumper may have to be changed as f ol l ows: •...
Page 341 Page 6.4 USER OPTIONS Vl Lines The Vectored Interrupt lines (Vl) are properly configured to operate in a Z-100 Family Computer; no interrupt jumpers are necessary. However, if you use the Controller Card in a non-standard configuration, configure Vl lines 0 through 7, as required, by installing the necessary jumper wires.
Page 342 I/O address BASE + 5 . Z enith software currently uses switch section 0 for 48/96 tpi drive selection. The remaining ¹2 switch position is not used ZENITH COMPUTERS DESCRIPTION SWITCH SECTION (With 5-1/4", 48 TPI Drives)
Page 343: Other Options
Page 6.6 USER OPTIONS Other Options Other jumpers may be required if you change to different type disk drives and recalibration ever becomes necessary. See the "Calibration" section of this Manual for the use of those jum- pers.
Page 344: Programming Data
Page 6.7 PROGRA M M ING DATA This section contains reference tables and data for the pro- grammer who wishes to write software for his Floppy Disk Controller. These tables should be used in conjunction with the 1797 disk controller data sheet (in the rear of this Manual) for complete programming information.
Page 345 Page 6.8 PROGRA M M ING DATA SWITCH DESCRIPTION Z E N ITH COMPUTERS SECTION I (With 5-1/4", 48 TPI Drives) PORT ADDRESS (MSB) o > CID ~ C&~ (LSB) Q 3 ~ Undefined Status port bit 4 Status port bit 3 Pictorial 6-4 DIP Switch Definitions Port Bit Definitions...
Page 346 Page 6.9 PROGRA M M ING DATA Control Latch Bit Definitions FUNCTION SIGNAL NAME BIT NO. Select drive 1 DSA,DSB Select drive 2 Select drive 3 Select drive 4 0 = Select 5.25" Select 8" Deselect all drives DSEN 1 = Select drive specified by bits 0, 1, and 2 PRECOMP 5.25"...
Page 347 Page 6.10 PROGRA M M ING DATA Status Port Bit Definitions FUNCTION BIT NO. SIGNAL NAME No interrupt request INTRQ 1 = Interrupt request from 1797 MOTORON (5") Delay not active running Delay active DON'T CARE Not defined Set by section 0 of DIP 96TPI switch on Floppy Disk Controller Card...
Page 348 Page 6.11 PROGRA M M ING DATA Precompensation Options The following chart lists the signal and jumper requirements to implement the desired write precompensation options for each type of diskette format. Signal and Jumper Requirements TYPE OF DRIVE NO TRACKS ALL TRACKS TRACKS) 43 8"...
Page 349 (We recommend that track 0, side 0 o f a d o u ble-density 8" diskette be recorded in single-density in compliance with the IBM double-density format.) Zenith software conventions currently use the Card's DIP switch section 0 (status port bit 3) to specify 5.25" drive's track density(0 = 96 tpi).
Page 350: Drive Interface Connectors
Page 6.13 PROGRA M M ING DATA Drive Interface Connectors 5-1/4" Drive Connector (P2) NOTE: All signals are active low at the connectors. D ESC R IPTION (NC) Active read filter (NC) TD use control Drive select 3 Index/sector Drive select 0 Drive select 1 Drive select 2 P2 CONNECTOR...
Page 351 Page 6.14 PROGRA M M ING DATA Drive Interface Connectors 8" Drive Connector (P1) NOTE: All signals are active low at the connector. DESCRIPTION DESC R I PTION Drive s e lect 0 Head current switch/ G ND active read filter Driv e s e l ect 1 G ND (NC) Not assigned...
Page 352 Page 6.15 PROGRA M M ING DATA S-100 BUS CONNECTOR P IN SIG N A L P IN SIGNA L SIGNAL +8 volts DO1/Data Out 1 (NC) RFU +16 volts DOO/Data Out 0 (NC) XRDY (NC) A10 (NC) RFU 2 3 4 5 6 7 DO4/Data Out 4 DO5/Data Out 5 (NC) INT...
Page 353 page 6.16 PROGRA M M ING DATA Sample Programs SHOWN HERE ARE EXAMPLES OF THE TYPE OF ASSEMBLY LANGUAGE CODE REQUIRED FOR COMMON OPERATIONS WITH THE H/Z-207 DISK CONTROLLER. IN ALL CASES, IT IS ASSUMED THAT THE DRIVE, DENSITY AND PRECOMP HAVE BEEN SELECTED AND THAT WAIT STATES ARE ENABLED PRIOR TO ANY ATTEMPT TO READ/WRITE/SEEK A PARTICULAR DRIVE THROUGH A WRITE OF THE APPROPRIATE DATA TO THE H/Z —...
Page 354 Dp >p • • • • • • • • • • • • • 4< • • • • • .Ir ! COMPONENT BOTTOM SIDE S IDE "' JJ cs .0. • • • • • • OX • •...
Page 355: Block Diagram
STATUS PORT T E R F CONTROL 5.25 LATCH 1797 DATA SEPARATION WR ITE PRECOMPEN- SATION BLOCK DIAGRAM...
Page 356 page 6.17 PROGRA M M ING DATA 0080 ASDRQ E QU ;DRQ LINE FROM 1797 MISC EQUATES SECSIZ EQU 0100 ;ASSUMED SECTOR SIZE FOR THE EXAMPLES DATA AREAS 1000 1000H ;ASSUMED DATA AREA FOR EXAMPLES 1000 BUFF >BUFFER 1 100 SECT ;ASSUMED LOCATION OF SECTOR TO READ/WRITE 1 101...
Page 357 page 6.18 PROGRA M M ING DATA 0000 3A0011 READ: LD A SECT ;GET SECTOR TO READ 0003 D3B2 FDSEC ;WRITE SECTOR TO 1797 SECTOR REGISTER 0005 210010 ;POINT TO DATA BUFFER TO BE FILLED H>BUFF 0008 110001 D,SECSIZ ; SECTOR SIZE IN D , E OOOB 3EBB A,BBH ;READ SECTOR COMMAND (SEE ABOVE)
Page 358 page 6.19 PROGRA M M ING DATA Write a Sector WRITE A SECTOR THE SECTOR WRITE OPERATION IS SIMILAR TO THE READ OPERATION DESCRIBED PREVIOUSLY. I N THE EXAMPLE BELOW, THE WRITE COMMAND IS HARD CODED AS OA8H. AS BEFORE> VARIOUS BITS IN THIS COMMAND CONTROL THE WRITE OPERATION PARAMETERS AS DESCRIBED IN THE 1797 DATA SHEET, AND IN PRACTICE IT WILL BE NECESSARY TO DETERMINE SOME OF THE BITS DYNAMICALLY.
Page 359 page 6.20 PROGRA M M ING DATA Seek a Track SEEK A TRACK THE SEEK OPERATION (MOVING THE HEAD) IS ACCOMPLISHED BY LOADING THE DESIRED TRACK INTO THE DATA REGISTER AND 1SSUING THE SEEK COMMAND. IN EXECUTING THE SEEK COMMAND> THE 1797 IS ASSUMED TO HAVE THE TRACK NUMBER OF THE TRACK OVER WHICH THE HEAD IS CURRENTLY POSITIONED IN THE TRACK REGISTER.
Page 360: Theory Of Operation
Page 6.21 THEORY OF OPERATION Refer to the B l ock D i agram ( Fold-out from P age 6 . 16), as you read the following description. The Block Diagram of the Floppy Disk Controller Card consists of seven parts: the bus interface, the status port, the control latch, the 1797 floppy disk controller, the data separation and write precompensation circuitry, and the two drive interfaces.
Page 361 Page 6.22 THEORY OF OPERATION Control Latch The control latch accepts commands to the disk drives such as DRIVE SELECT, 5" FASTEP, and others that have to do with the selection and mode of the drives. Definitions of the control bits are listed in the detailed circuit description. 1797 Controller The 1797 controls the placement of information on the disk- ette.
Page 362: Circuit Description
Page 6.23 DETAILED CIRCUIT DESCRIPTION Before you read the rest of this section, you should review the data sheets for the 1797, 1691, and 2143 integrated cir- cuits in Appendix D. Then refer to the schematic drawing while you read the following information. S-100 Bus Interface The S-100 bus interface is compatible with any IEEE 696 S- 100 bus.
Page 363 Page 6.24 DETAILED CIRCUIT DESCRIPTION Address Lines The address lines from the bus enter the Card through pins 29-31 and 79-83 of the bus interface. They are buffered by the 74LS244 IC, U34. Control Lines The control lines from the S-100 bus enter the board through pins 24, 25, 45, 46, and 75-78 of the bus interface.
Page 364 Page 6.25 DETAILED CIRCUIT DESCRIPTION The reset state for the 1797 is a 03H in the command register, a 01H in th e s e ctor register, a 0 i n t h e N o t R e ady bit (bit 7) of the status register, and a restore command execution.
Page 365 Page 6.26 DETAILED CIRCUIT DESCRIPTION Read Status Latch (U31) Assume that a status signal needs to be read. There are two sources of status information for the S-100 bus, the status port and the status register in the 1797. To read the status port, the following happens.
Page 366 page 6.27 DETAILED CIRCUIT DESCRIPTION Read Status Register of 1797 (U22) Assume now that the 1797's status register is to be read. The procedure is the same as the above, except that address lines AO, A1, and A2 are low. Because the address bits AO-A2 are different, the I/O address decoder (U17) does not enable the status latch (U31).
Page 367 Page 6.28 DETAILED CIRCUIT DESCRIPTION At the completion of the access delay, the wait state is cleared, RDY is asserted, and the CPU completes the read or write of the data register in the 1797. A RESET or an INTRQ signal also clears the wait state, so that the CPU does not hang up after an error during a disk access.
Page 368 J1, post E. For most 6-MHz operation, J1 is connected between post E and post F. For the Z-100 series of Computers, the Computer's internal timing requires that the 6-MHz jumper be used. Data Shaping Data pulses to the drive are reshaped by U16, a one-shot multivibrator, to 400 ns.
Page 369: Drive Interfaces
Page 6.30 DETAILED CIRCUIT DESCRIPTION Data Separation and Precompensation Data separation and precompensation are performed primarily by U1, U3, U5, U4, U16, and U22. Almost all of these two functions are internal to these IC's. Therefore, an understand- ing of the functions requires a careful study of the IC's data sheets.
Page 370 Page 6.31 DETAILED CIRCUIT DESCRIPTION 8" Drive Interface The 8" drive interface, which is designed for use with a stan- dard 50-pin Shugart-compatable (SA801 or SA851) disk drive, connects to the drives cable through P1. All output signals to the drives are buffered through U8 and U10 except WG and HEADLOAD.
Page 371: Troubleshooting
• Yo u r local Zenith Data Systems Dealer; • Th e n e a rest Authorized Zenith Data Systems Service Center (check the list accompanying this product or look in the yellow pages under "Data Processing Equipment" ); •...
Page 372: Troubleshooting Chart
Troubleshooting Chart If you want to service your Card yourself instead of sending it to Zenith or Heath for servicing, check the chart below for possible causes to the problems your Card may be having. PROBLEM POSSIBLE CAUSE Drive access light does not turn on when diskette is booted.
Page 373: Calibration
CALIBRATION If you have an assembled Disk Controller Card, it has been calibrated at the factory to operate properly with Zenith Data Systems (ZDS) and Heath disk drives. Therefore, if you are using ZDS/Heath Equipment, you probably will not need to re- calibrate your assembled Controller Card.
Page 374 "' G'ND/ ' o' Ij~ QQQQQQQQQ Q Q Q Q Q Q Q Q ' Q XXQXXQQXQ Q Q amzm ~ PICTORIAL 6-5 Caiibration Locations...
Page 375 I f the value o f p r e compensation is h i gher fo r th e 8 " drives, or if you have only 8" drives, go to Step 6. All Heath/Zenith floppy drives require 120 ns of write pre- compensation.
Page 376 Page 6.36 CALI B RATION Fo rm a t t h e 5 .25" diskette. While FORMAT is running, turn R4 to adjust the pulse width displayed on the oscil- loscope to the value of write precompensation needed by your 5.25" drives. Proceed now to Step 15. If y o u h a v e both 5.25"...
Page 377 Page 6.37 CALIBRATION Data Separator Calibration Perform the calibration as follows: Tu r n the Computer on. Allow at least five minutes for the Disk Controller Card to r e ach operating tempera- ture. Ma k e sure the disk drives are not selected. Se t the DVM's voltage range to 2 V.
Page 378 Page 6.38 REPLACEMENT PARTS LIST CIRCUIT HEA T H DESCR I PTION CIRCUIT HEA T H DESCR I PTION Comp. No. P a rt No. Comp. No. P a rt No. Resistors Capacitors (cont'd) All resistors are 1/4 W, 5%, unless specified otherwise. C4-C6 25-220 10 tLF tantalum...
Page 379 Page 6.39 SEMICONDUCTOR IDENTIFICATION This section is divided into two parts; "Component Number Index" and Part Number Index." The first section provides a cross-reference between semiconductor component numbers and their respective Part Numbers. The component numbers are listed in numerical order. The second section provides a lead configuration detail (basing diagram) for each semicon- ductor Part Number.
Page 380 Page 6.40 SEMICONDUCTOR IDENTIFICATION Part Number Index This index shows a lead configuration detail (basing diagram) of each semiconductor part number. Diodes HEATH MAY BE DESCRIPTION PART REPLACED LEAD CONFIGURATION (TOP VIEW) NUMBER WITH INDORIANT TNI IANDFO FNO Of DIODFS CAN li NARN[D IN A NON •...
Page 381 page 6.41 SEMICONDUCTOR IDENTIFICATION Integrated Circuits HEATH MAY BE PART REPLACED DESCRIPTION LEAD CONFIGURATION NUMBER WITH (TOP VIEW) 442-54 UA 7805 + 5 V REGULATOR 442-663 LM 78M12 + 12 V REGULATOR C OAI C ONI VOU7 ADJUSTABLE 442-708 V IN REGULATOR ADJ.
Page 382 page 6.42 SEMICONDUCTOR IDENTIF ICATION Integrated Circuits (Cont'd) HEATH MAY BE LEAD CONFIGURATION PART DESCRIPTION REPLACED (TOP VIEW) NUMBER WITH 443-728 74LSOO QUAD NANDS Vcc 2 CLR 2P R C LR CK PR 74LS74 DUAL D CK PR'" 0 C L R 0 FLIP-FLOPS I CLR I CK...
Page 383 page 6.43 SEMICONDUCTOR IDENTIFICATION Integrated Circuits (Cont'd) HEATH MAY BE PART REPLACED DESCRIPTION LEAD CONFIGURATION NUMBER WITH (TOP VIEW) I IA 443-779 74LS02 QUAD NORS Gi N D 2 A2 I Y 4 443-791 74LS244 TRI-STATE BUFFER/DRIVERS I A I 2 A4 I A 2 2 Y 3 IA3 G ND...
Page 384 Page 6.44 SEMICONDUCTOR IDENTIFICATION Integrated Circuits (Cont'd} HEATH MAY BE PART DESCRIPTION REPLACED LEAD CONFIGURATION NUMBER (TOP VIEW) WITH TRIPLE 3-INPUT 443-800 74LS27 NORS G i N D V cc 8 Q CL O C K 443-805 74LS273 CLEAR CLEAR CLEAR CLEAR OCTAL D...
Page 385 page 6.45 SEMICONDUCTOR IDENTIFICATION Integrated Circuits (Cont'd) HEATH MAY BE PART REPLACED DESCRIPTION LEAD CONFIGURATION NUMBER WITH (TOP VIEW) ENABLE OE ' 0 OE OE 0 443-863 74LS374 OCTAL D TRI-STATE FLIP-FLOP OUTPUT 10 G ND CONTR OI 443-875 74LS32 QUAD 2-INPUT DATA OUTPUTS 3-line...
Page 386 Page 6.46 SEMICONDUCTOR IDENTIFICATION o nt'd) Integrated Circuits (C HEATH MAY BE PART REPLACED DESCRIPTION LEAD CONFIGURATION NUMBER WITH (TOP VIEW) 443-971 74LS688 8-BIT COMPARATOR i')' G i '90 Ci" 4 0 39 38 3 7 3 6 3 5 34 33 3 2 31 30 29 Z 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 FLOPPY 443-997...
Page 387 page 6.47 SEMICONDUCTOR IDENTIFICATION Integrated Circuits (Cont'd) HEATH MAY BE PART REPLACED LEAD CONFIGURATION DESCRIPTION (TOP VIEW) NUMBER WITH FRED CC OU T P UT CC COiNTROL VOLTAGE FREQ CO i N TROL CONTROLLED 443-999 74LS624 RANGEC OSCILLATOR CX 2 E NABLE Y G ND G ND RANGE CXI OUTPUT...
Page 388 page 6.48 SEMICONDUCTOR IDENTIF ICATION Integrated Circuits (Cont'd) HEATH MAY BE LEAD CONFIGURATION REPLACED DESCRIPTION PART (TOP YIEW) NUMBER WITH R X2 C D 2 443-1040 S6LS02 MULTIVIBRATQR Gl'!D ' lXI 443-1063 74LS33 QUAD 2-INP UT BUFFER Gh !0...
Page 389: Circuit Board X-Ray View
page 6.49 CIRCUIT BOARD X-RAY VIEW NOTE: To find the PART NUMBER of a component for the pur- pose of ordering a replacement part: F i nd the circuit component number (R13, R14, etc.) on the X-Ray View. B. L o cate this same number in the "Circuit Component Number"...
Page 390 . ': Ri TG43 R~19 ~ U1 & I,. Z CIRCUIT I (Shown from the c{ component...
Page 391 ' U22 ':1'28888 CIRCUIT BOARD X-RAY VIEW from the component side. The foil on the ;omponent side is shown in red.)
Page 392: Interconnect Pin And Signal Definitions
Page 6.50 INTERCONNECT PIN AND SIGNAL DEFINITIONS Refer to the Schematic and pages 6.13-6.15 for pin and signal numbers. Address bits. AO-A7 Address latch enable. Data and address lines from the CPU have valid information. The H/Z-207 board is selected (enabled). BDSEL Clock signal.
Page 393 Page 6.51 INTERCONNECT PIN AND SIGNAL DEFINITIONS Head load. Head load timing. The drive head is not engaged when this signal is low. INDEX The index hole on the diskette has been detected. Interrupt request. H/Z-207 board has input INTRQ for the CPU.
Page 394 page 6.52 INTERCONNECT PIN AND SIGNAL DEFINITIONS Data and clock stream from the drive. Data or status signals input for the bus are RDME enabled. Slave board is ready. (The H/Z-207 board is a slave board.) Read enable. Enables the 179? chip for read operations when low.
Page 395 Page 6.53 INTERCONNECT PIN AND SIGNAL DEFINITIONS VFO enable/write fault. When WG is as- VFOE/WF serted, VFOE/WF flags write faults when d easserted, terminating an y w r ite c o m - mand. When W G i s d e a s serted, VFOE/ W F enables th e d a t a s e p a rator i n t h e 1691.
Page 396 Page 6.54 INTERCONNECT PIN AND SIGNAL DEFINITIONS Precompensated write data pulses that WR DATA have been reshaped by U16. 5DSO-5DS3 Five- i nch drive select signals. 5"FASTSTEP Enables fast stepping in the 5.25" drives. 8"/5" Selects between the 8" and the 5 .25" drives.
Page 397 Page 7.1 5-1/4" Floppy Drives Description Programming Cable Connections Operation...
Page 398: Description
Page 7.2 DESCRIPTION The Z-207-3 5-1/4" Floppy Drive is a mass storage device that stores programs and information for your computer. Information is stored on two sides of a 5.25-inch, oxide-coated diskette with 40 tracks per side. This drive is capable of dou- ble-density operation when it is used with a double-density controller, like the one supplied in the H/Z-100 family com- puters.
Page 399: Programming
page 7.3 P ROG RAMMING HARDWARE UNIT ZERO INSET TERMINATOR NETI",OP K IIIIIIIIIttIIII.IIIIIIIII ff. VV BA I 7 I 7 I7 I7 I7 17 1 1 1 1 1 1 I7 I7 a a I7 I7 I7 1=1 1-1-1 -'1 =l n -1 Ll 1 7 7 7 7 7 - 7 I-1=l-1:I-1-1-1 I-1-1-1-1-I i...
Page 400 Page 7.4 PROGRAMMING Programming Pl Refer to Pictorial 7-1 for the following steps. • If t h i s Drive is to be hardware unit 0, cut the program- ming plug as shown in Part A of the Pictorial. • If t h i s Drive is to be hardware unit 1, cut the program- ming plug as shown in Part B of the Pictorial.
Page 401: Cable Connections
Page 7.5 CABLE CONNECTIONS Refer to Pictorial 7-3 for a view of cable connections. FLOPPY DR IVE UN IT POWER PLUG " L4yy L L L L L L L L L SMALL TRIANGLE MARKED EDGE Pictorial 7-3 Connecting Drive Cables...
Page 402: Operation
Page 7.6 OPERATION Diskette Loading Refer to Pictorial 7-4, open the front panel door, and insert the diskette with the label up as shown. Then close the door. Diskette Handling The diskette can be easily damaged. Handle it carefully as fol- lows: Ke e p the diskette in its storage envelope whenever it is not in the Floppy Disk drive.
Page 403 Page 7.7 OPERATION Write-Protect This diskette can be write protected so that it cannot be written on. To do this, cover the side notch with a tab or opaque tape. See Pictorial 7-5. READ-WRITE ACCESS SLOT WR ITE-.;. ENABLE, TAB OR NOTCH:;...
Page 405: Power Supply
Page 8.1 Power Supply Power Line Considerations Specifications...
Page 406: Power Line Considerations
page 8.2 POWER LINE CONSIDERATIONS The power supply is a line-operated, voltage-fed, half-bridge, switching-type power supply. It first converts the AC line volt- age to direct current and then chops this DC into a quasi- squarewave. This squarewave drives the primary of an inver- ter transformer.
Page 407: Specifications
Page 8.3 SPECIFICATIONS 100 — 130 VAC, 60 Hz; AC Input Voltage .. 200 — 260 VAC, 50 Hz; switch selectable Temperature Range 10 degrees C to 50 degrees C. 16 milliseconds at full load. H old Up Time . . Current Limiting .
Page 408 Additional + 12 VDC ~ 5% output at 1. 5 amperes maximum. Ripple: 50 mV peak-to-peak maximum. Zenith Data Systems reserves the right to discontinue products and to change specifications at any time without incurring any obligation to incorporate new features in products previously...
Page 409 Page 9.1 Chassis, Cabinet, &. Cables Replacement Parts List Cables Location/Description 9.12 Circuit Boards 8 H a r d w are 9.17...
Page 410 Page 9.2 REPLACEMENT PARTS LIST This Replacement Parts List includes the Z-100 All-in-One model and the Z-100 Low Profile model. Exploded Views Cables Hardware Circuit Boards Circuit Board Parts Refer to the Parts List that corresponds to your Computer (Low-Profile or All-ln-One). All-In-One Model The following Key Numbers correspond to the numbers on the All-in One parts pictorials.
Page 411 page 9.3 REPLACEMENT PARTS LIST I ) ~t / //// / / / // /////////// ' ALL-IN-ONE...
Page 412 page 9.4 REPLACEMENT PARTS LIST KEY PART DESCRIPTION NO. NO. 34-conductor cable (disk drive 134 - 1 247 to disk controller board) 200-1419 Drive chassis mounting plate 250-1264 6-32 x 3/8" hex head screw Disk drive (5 1/4" 48 tpi) 150-142 Drive panel 203-2129...
Page 413 page 9-5 REPLACEMENT PARTS LIST KEY PART DESCRIPTION NO. NO. 73-6 Grommet 204-2606 CRT support bracket 250-1264 6-32 x 3/8" hex head screw 250-1318 ¹10 x 1-1/2" hex head screw 253-98 ¹10 flat washer CRT 12" green phosphor 234-297 CRT 12" white phosphor 234-296 234-295 CRT 12"...
Page 414 Page 9.6 REPLACEMENT PARTS LIST PART DESCRIPTION S-100 card cage 206-1416 94-631 S-100 card rack 203-2139-1 Back panel ¹4 lockwasher 254-9 252-2 Large 4-40 nut Floppy cable — 8" drive — 50 conductor 134-1330 134-1254 Cable — RGB out Control — 500 0 10-1192 1/4"...
Page 415 Page 9.7 ACE5fENT p4RTS L > ~4 6 4 0 » ~ 52...
Page 416 Page 9.8 REPLACEMENT PARTS LIST Low Profile Model The following Key Numbers correspond to the numbers on the Parts Pictorials. ns indicates part not shown. KEY PART DE SC R IPT ION NO. NO. Top cover 92-758 Slide rail 204-2605 2 ns 258-750 Spring...
Page 417 page 9.9 REPLACEMENT PARTS LIST 1II~ / // / /l.!/ I ~ j j...
Page 418 page 9.10 REPLACEMENT PARTS LIST KEY PART DESCRIPTION NO. NO. 7-conductor video RGB cable 134-1254 134-1330 50-conductor flat cable 252-2 Large 4-40 nut 254-9 P4 lockwasher 94-631 Card rack 206-1416 Card cage 200-1418-1 Chassis 254-6 P6 washer 203-2139-1 Back panel 250-1307 4r6 x 1/4"...
Page 420: Cables Location/Description
page 9.12 CABLES LOCATION/DESCRIPTION CABLES PART NO. DESCRIPTION 134-1330 50-conductor flat cable. From J16 on the rear panel to P1 on the disk controller board. 134-1257 40-conductor flat cable. From P304 and P305 on the video logic board to P104 and P106 on the main board. 34-conductor flat cable.
Page 421 Page 9.13 CABLES LOCATION/DESCRIPTION The following lists provide you with a description and location of the cables and connectors used in your Z-100 l ow-Profile or All-In-One Computer. Part numbers for these cables are listed in the Replacement Parts List in this manual. Power Supply r r c c CGCCC...
Page 422 Page 9.14 CABLES LOCATION/DESCRIPTION Video Logic Board VIDEO LOGIC CIRCUIT BOARD .MARKED :.:,.EDGE I Pictorial 9-2 Video Logic Cables 40-conductor cable from plug P104 to the main board plug P304. Part number 134-1257. 40-conductor cable from plug P106 to the main board plug P305.
Page 423 Page 9.15 CABLES LOCATION/DESCRIPTION Keyboard X !~I AI A IN KEYBOARD „ v " Pictorial 9-3 Keyboard Cables 20-conductor flex cable to the main board plug P105 10-conductor flex cable to the main board plug P107...
Page 424 Page 9.f6 CABLES LOCATION/DESCRIPTION Video Deflection Board BLACK To POWER SUPPLY YELLOW ORANGE HOR Z E BROWN YELL W TO V I DEO LOGIC BOARD YO K TO HORIZONTAL YOKE BLACK To VERTICAL YOKE VERT ~YOKE Pictorial 9-4 Video Deflection Cables 6-wire socket from the power supply and video board to the 10-pin plug on the video deflection board 2-wire socket from the horizontal yoke to the video deflection...
Page 425 page 9.17 C IRCUIT BOARDS 8 HARDW A R E Circuit Boards PART NO. DESCRIPTION 181-3630 Main board (8K ROM) 181-4106 Main board (16K ROM) 181-3631 Video logic board (B/W) 181-3267 Video logic board (color) 181-3763 Floppy disk controller board 234-202 Video deflection board Hardware...
Page 427 Page 10.1 Programming Data Description General Information Devices Permitting User Programming Port Addresses Z-DOS Initialization Sequence ASCII Chart 10.30 Escape Codes 10.38 Escape Codes Defined 10.42 Key Code Chart 10.52 Keypad Code Chart 10.59 Function Key Code Chart 10.60...
Page 428: Description
page 10.2 DESCRIPTION This section of the Manual provides condensed system pro- gramming information. It is provided for the experienced pro- grammer to help him understand the Computer System so he can develop his own software or firmware.
Page 429: General Information
Page 10.3 GENERAL INFORMATION 8085 Key Facts Clock Speed: 5 MHz. Address Space: 16 bits extended to 24. Interrupts: (NMI or p o wer f ailure) TRAP RST5.5, RST6.5, RST7.5 disabled. Vectored interrupts through 8259 dis- abled by Mask. External devices, a n d p r o cessor DMA: swap.
Page 430 Page 10.4 GENERAL INFORMATION Interrupt structure Device Type: 8259A. Master standard; slave optional. Number: LEVELS MASTER Parity error or (S-100 pin 98). 0 (Highest) Error Processor swap interrupt. Timer (8253 Out 0 or Out 2). Slave 8259. Serial port A. Serial port B.
Page 431 Page 10.5 GENERAL INFORMATION Processor Swapping The Computer contains two processors, with selection cir- cuitry to enable the desired processor. Processor swap occurs when the presently selected processor writes to bit 7 (MSB) of the processor swap port (PSP). A 1 selects the 8088 and a 0 selects the 8085.
Page 432: Memory Mapping
page 10.6 GENERAL INFORMATION Memory Mapping Four options affect how the ROM is addressed. These options are enabled when the program writes to the memory control latch (MEMCTL). Latch bits 2 and 3 control the four options MSB). The MEMCTL latch is at port FC. (bit 3 The first option is used for power up.
Page 433 Page 10.7 GENERAL INFORMATION RAM normally consists of from one to three banks of 64K bytes. This provides from 64 to 192K bytes of memory. The RAM address configuration depends on the map control bits in MEMCTL. Bit 0 is MAPSELO and bit 1 is MAPSEL1. The following chart shows which port bits control the various RAM configuration.
Page 434 Page 10.8 GENERAL INFORMATION The KILL P ARITY option disables the parity checking cir- cuitry. This option is enabled when the system writes a 0 to bit 5 of the MEMCTL port. It also clears a parity error by first writing a 0 to bit 5 of the port and then a 1 to bit 5 of the port.
Page 435 Page 10.9 GENERAL INFORMATION The 8253 data sheet is supplied in the Appendices portion of this documentation. The following chart is provided for the convenience of those who may already be familiar with the 8253 device. DEFIN I TION = Use 16-bit binary counter 1 = Use 4-decade binary coded decimal counter = M o d e 0 Mode1...
Page 436: Devices Permitting User Programming
Page 10.10 DEVICES PERMITTING USER PROGR A M M ING Several of the major IC's in your Computer are user pro- grammable. Please refer to the manufacturer's data sheets in the Appendices portion of this documentation for pro- gramming information. These IC's include: 8259's Interrupt controllers 6845...
Page 437: Port Addresses
Page 10.11 PORT ADDRESSES The following chart lists the input/output port assignments for the H/Z-100 series computers. Port Address in hexadecimal Device DIP Switch SW101 Processor Swap Port High Address Latch Memory Control Latch 8253 Timer Status reserved by ZDS...
Page 438 Page 10.12 PORT ADDRESSES Device Port Address in hexadecimal Gateway (reserved) OA4-OA7 Network Card (NET-100) OAO-OA3 Expansion Memory Boards (Z-205) 098-09F 084-097 reserved by ZDS 080-083 Development Port (Temporary) 060-07F Primary Multiport Card (Z-204) Secondary Multiport Card (Z-204) 040-05F reserved for non-ZDS vendors 000-03F Memory Assignments Device...
Page 439 Page 10.13 PORT ADDRESSES Parallel Port The parallel port is d esigned around U114 (68A21), the Peripheral Interface Adapter. The IC performs three functions: It operates as a printer port, it serves as a port for the light pen and it couples the video board vertical retrace signal to the CPU.
Page 440: Z-Dos Initialization Sequence
Page 10.14 Z-DOS INITIALIZATION SEQUENCE This section describes all phases of Z-DOS initialization from the time that control is passed from the system ROM until Z-DOS gives control to COMMAND.COM for standard system operation. Following the initialization description are some sample initialization programs.
Page 441 Page 10.15 Z-DOS INITIALIZATION SEQUENCE The system ROM loads in the loader at address 0:400. The contents of the instruction pointer (IP) is therefore 400, and the code segment (CS) register is 0. The other registers are assumed to contain random data. The loader assumes that the system ROM read is enough of track zero so as to have at least the first sector of the director already in RAM.
Page 442 Page 10.16 Z-DOS INITIALIZATION SEQUENCE Secondly, the loader sets up the registers into the 8080 mem- ory model (CS DS = SS ES) and proceeds to collect infor- mation passed to it by the system ROM. This information in- cludes boot device number, port address, and boot string. It then locates the ROM to the top of the 8088 address space.
Page 443 Page 10.17 Z-DOS INITIALIZATION SEQUENCE The specific disk layouts for the different diskette formats is as follows. The first number is the starting sector number, and the number in parenthesis is the size in sectors. 8" ss 8" ds 48 ss 48 ds Loader o (4)
Page 444 page 10.18 Z-DOS INITIALIZATION SEQUENCE IO.SYS IO.SYS is entered at address 40:0, with Sl pointing to the disk parameter table contained in the loader (see the following table). Th e I O .SYS i n sures a n 8 0 8 0 m e m ory m o del DS = ES = SS), and then sets its stack pointer to a mem- ory address in the IO.SYS workspace.
Page 445 Page 10.19 Z-DOS INITIALIZATION SEQUENCE IO.SYS next moves the ROM work space to the IO.SYS's workspace, so that it will not conflict with other pieces of the system. Then the IO.SYS performs as follows: T h e interrupt vectors are all initialized to the default interrupt handler address, the wild interrupt hand- ler.
Page 446 Page 10.20 Z-DOS INITIALIZATION SEQUENCE T h e t imer is then initialized, and a test is made to insure that the timer is functioning properly. T h e slave 8259A is set for level-triggered cascad- ing, and the 8086 interrupt is set to fully nested and non-buffered.
Page 447 Page 10.21 Z-DOS INITIALIZATION SEQUENCE Z-DOS Drive Mapping For each 5-1/4" and 8" drive in the system, IO.SYS restores the drive head. If it sees an invalid track zero indication, it marks the drive as imaginary in the drive table. Otherwise, it issues "10 steps out"...
Page 448 page 10.22 Z-DOS INITIALIZATION SEQUENCE The next address for the final location for the file Z-DOS.SYS is found by adding the total size of IO.SYS and its required work areas. Then the file Z-DOS.SYS is searched for in the directory. Z-DOS.SYS must be the second name in the direc- tory for IO.SYS to be able to locate it.
Page 449 Page 10.23 Z-DOS INITIALIZATION SEQUENCE On return from DOS INIT, IO.SYS turns on the keyboard, and then uses the appropriate function calls to load and exe- cute the file COMMAND.COM. Once COMMAND.COM is loaded, control is passed to it, at which point it initializes itself, prints its header, checks for AUTOEXEC.BAT, gets the date and time from the user, and prints the system prompt.
Page 450 Page 10.24 Z-DOS INITIALIZATION SEQUENCE Sample Programs NOTE: Label definitions for the following programs can be found in the Z-DOS Distribution Disk II definitions files, or in Appendix I of Volume II of the Z-DOS Manual.
Page 451 Page 10.25 Z-DOS INITIALIZATION SEQUENCE Initialize the Keyboard AL,ZKEYDK Disable keyboard until ready ZKEYBRDC,AL BINITKEY1: Wait for command to complete AL,ZKEYBRDS TEST AL,ZKEYIBF BIN ITKE Y1 Flush typeahead buffer AL,ZKEYCF ZKEYBRDC,AL AL,ZKEYBRDD S ave vi d e o state set up by the ROM monitor AL,ZVIDEO+PIADATA ;...
Page 452 Page 10.26 Z-DOS INITIALIZATION SEQUENCE Initialize PIA port AL,PIADDAC Set control ports for data ZPIA+PIACTLA,AL ZPIA+PIACTLB,AL AL, 01011111B Load initial data value for port A ZPIA+PIADATA,AL AL, 11111111B Load initial data value for port B ZPIA+PIADATB,AL AL,AL Set control ports for direction ZPIA+PIACTLA,AL ZPIA+PIACTLB,AL AL, 10101111B...
Page 453 Page 10.27 Z-DOS INITIALIZATION SEQUENCE AL,ZTIMER+PITC1 AL,ZTIMER+PITC1 AL,ZTIMER+PITC2 AL,ZTIMER~PITC2 Init counter modes AL,PITSCO+PITRLW+PITMSW ZTIMER+PITCW,AL ; Counter 0 — square wave generator AL,PITSC1+PITRLW+PITMITC ZTIMER+PITCW,AL ; Counter 1 — event counter AL,PITSC2+PITRLW+PITMITC ZTIMER+PITCW,AL ; Counter 2 — intr on terminal count Init counter values Timer 1 AL,AL ZTIMER+PITC1,AL...
Page 454 Page 10.28 Z-DOS INITIALIZATION SEQUENCE CX,Z205BMC C X = number o f b o a r d s MEMILO: Set i t DX, AL LOOP MEMILO AX, AX Start at segment 0 MEM IL: S et u p s e gment r e g s DS, AX ES, AX AX,DS:0...
Page 455 Page 10.29 Z-DOS INITIALIZATION SEQUENCE AL,ICW3S3 ZM8259A+ICW3,AL ; Slave is connected to line 3 AL,ICW4UPM+ICW4SFN special fully nested, nonbuf fered ZM8259A+ICW4, AL; Set processor to 8088, AL,NOT (OCW1IMO OR OCW1IM2 OR OCW1IM4 OR OCW1IM5 OR OCW1IM6) ZM8259A+OCW1,AL ; Allow Fatal hardware, timer, serial A, serial B, and keyboard/video interrupts...
Page 456: Ascii Chart
Page 10.30 ASCII CHART CHAR CTRL DESCRIPTION Null, tape feed. Start of Heading. Start of text. End of text. End of transmission. 2 3 4 5 6 7 8 C D E F ENQ ... Enquiry. Acknowledge. Rings Bell. B ACK Backspace;...
Page 457 Page 10.31 ASCII CHART DEC HEX CHAR KEY C T RL DESCRIPTION End of medium. Substitute. ESC ESC Escape. File separator. Group separator. Record separator. Unit separator. Space (Spacebar). Exclamation point. Quotation mark. Number sign. ¹ ¹ Dollar sign. Percent sign. &...
Page 458 Page 10.32 ASCII CHART KEY CTRL DESCRIPTION SYMBOL CHAR Equal sign. Greater than. Question mark. At sign. Letter A. Letter B. Letter C. Letter D. C D E F C D E F Letter E. Letter F. Letter G. G H I G H I Letter H.
Page 459 Page 10.33 ASCII CHART SYMBOL OCT DEC HEX CHAR KEY CTRL DESCRIPTION ( I jt I jt tt) ( ltll l t l : I I I I l l : Underscore. 137 9 5 I l l l l : l i t ) Grave accent.
Page 460 Page 10.34 ASCII CHART SYMBOL OCT DEC HEX CHAR KEY CTRL DESCRIPTION I i i i i > 1 46 1 0 2 6 6 Letter f. I Il l • 147 103 6 7 Letter g. i l l « I •...
Page 461 Page 10.35 ASCII CHART SYMBOL OCT DEC HEX CHAR KEY CTRL DESCRIPTION <j i l 155 109 6 D Letter m. < Ij l l <j i l < j i l < I I I I (111 <Ill ( 111 ( I I I Letter n.
Page 462 Page 10.36 ASCII CHART SYMBOL OCT DEC HEX CHAR KEY CTRL DESCRIPTION 1 64 1 1 6 7 4 Letter t. I • Letter u. 1 1 7 7 5 ( 1i' I 0 I I I <t < Letter v. 1 1 8 7 6 I 4 I j I : t tl...
Page 463 Page 10.37 ASCII CHART SYMBOL OCT DEC HEX CHAR KEY CTRL DESCRIPTION Left brace. 1 73 1 2 3 7 B ( llll l l l l ' ( llllll l l ) ( l l ( l l ( l l Vertical bar (broken).
Page 464: Escape Codes
Page 10.38 ESCAPE CODES Cursor Functions ESC A Cursor up ESC B Cursor down ESC C Cursor right ESC D Cursor left ESC M Cursor home ESC I Reverse index ESC Y Direct cursor addressing ESC j Save cursor position ESC n Cursor position report Set cursor to previously saved position...
Page 465 Page 10.39 ESCAPE CODES Modes of Operation ESC F Enter graphics mode ESC G Exit graphics mode Enter alternate keypad mode ESC > Exit alternate keypad mode Enter reverse video mode ESC p Exit reverse video mode ESC q ESC t Enter keypad shifted mode ESC u Exit keypad shifted mode...
Page 466 Page 10.40 ESCAPE CODES ESCy Ps Reset modes Where Ps equals: Disable 25th line Enable key click Underscore cursor Cursor on Keypad unshifted Exit alternate keypad mode No auto line feed No auto CR Blinking cursor Enable keyboard auto repeat Disable key expansion Disable event driven (key up/down) mode...
Page 467 Page 10.41 ESCAPE CODES ESC ( Keyboard enable Escj Keyboard disable ESC v Wrap-around at end of line ESC w Discard at end of line ESC c Key Click The Computer will transmit the following sequences, but it will not respond to them if they are received by the Computer. ESC J Function Key FO ESC S...
Page 468 Page 10.42 ESCAPE CODES DEFINED Cursor Functions ESC A Cu rsor Up Moves the cursor up one line. If the cursor reaches the top line, it remains there, and no scrolling occurs. ESC B Cu rsor Down Moves the cursor down one line without changing columns. The cursor will not move past the bottom (24th) line and no scrolling will take place.
Page 469 Page 10.43 ESCAPE CODES DEFINED The first line and the left column are both 32<o (the smallest value of the printing characters) and increase from there. Since the lines are numbered from 1 to 25 (from top to bottom) and the columns from 1 to 80 (from left to right), you must add the proper line and column numbers to 31<0.
Page 470 Page 10.44 ESCAPE CODES DEFINED Erasing And Editing ESC E Cl ear Display And Home Cursor Erases the entire screen, fills the screen with spaces, and places the cursor in the home position. ESC J Er ase To End Of Page Erases all the information from the cursor (including the cursor position) to the end of the page.
Page 471 Page 10.45 ESCAPE CODES DEFINED ® En t er Insert Character Mode Lets you insert characters or words into text already displayed on the screen. As you type in new characters, existing text to the right of the cursor shifts to the right. As each new char- acter is inserted, the character at the end of the line is lost.
Page 472 Page 10.46 ESCAPE CODES DEFINED Modes Of Operation ESC F En ter Graphics Mode Enters the graphics mode to display any of the 33 special symbols (26 lower-case keys and seven other keys) that cor- respond to the graphic symbols. ESC 0 Ex i ts Graphics Mode Exits the graphics mode and returns to the display of normal...
Page 473 Page 10.47 ESCAPE CODES DEFINED ESC ) Ex i t Alternate Keypad Mode Exits the alternate keypad mode and returns to the transmis- sion of normal character codes. ESC p En ter Reverse Video Mode Enters the reverse video mode so that characters are dis- played as black characters on a white background.
Page 474 Page 10.48 ESCAPE CODES DEFINED Configuration ESC x Ps Set Modes Sets the following modes, where Ps equals: 1 = enable 25th line 2 = no key click 4 = block cursor 5= cursor off keypad shifted 7 = enter alternate keypad mode auto line feed on receipt of CR auto CR on receipt of line feed ;...
Page 475 Page 10.49 ESCAPE CODES DEFINED Additional Functions ESC z Reset To Power-Up Configuration Nullifies all previously set escape modes and returns to the power-up configuration. ESC Z Id entify As VT52 (ESC 1 K) The Computer responds to the interrogation with ESC/K to indicate that it can perform as VT52.
Page 476 Page 10.50 ESCAPE CODES DEFINED ESC m Fo re Back Specifies colors for foreground and background of display, where fore and back equal: black 1 = blue 2 = r e d magenta = green 5 = cyan = yellow 7 = white ESC { Ke yboard Enable Enables the keyboard after it was inhibited by an Keyboard...
Page 477 Page 10.51 ESCAPE CODES DEFINED ESC J Fu nction Key FO Transmits a unique escape code to perform a user-defined function. The computer will not respond to this code if it is received. ESC S Fu n ction Key F1 Same as above.
Page 478: Key Code Chart
Page 10.52 KEY CODE CHART After a key is detected as being down, the keyboard encoder places a byte on its data bus which represents only the de- pressed key. The codes for some of the keys depend on the state of the "modifier"...
Page 479 Page 10.53 KEY CODE CHART Control Control Caps Lock Down Shifted (Yes/No) Code Shift Code Shifted...
Page 480 Page 10.54 KEY CODE CHART Caps Lock Down Shifted Control Control Code (Yes/No) Shift Code Shifted BACK SPACE LINE FEED RETURN...
Page 481 Page 10.55 KEY CODE CHART Down Control Caps Lock Shifted Control (Yes/No) Code Code Shift Shifted SPACE...
Page 482 Page 10.56 KEY CODE CHART Down Shifted Control Control Caps Lock (Yes/No) Code Code Shifted Shift DELETE ENTER HELP...
Page 483 Page 1 0.57 KEY CODE CHART Shifted Control Control Caps Lock Down (Yes/No) Code Shifted Shift Code D CHR ICHR D LINE I LINE (up arrow) (down arrow) (right arrow) (left arrow) HOME BREAK -(keypad) (keypad) 0 (keypad) 1(keypad) 2 (keypad) 3 (keypad) 4 (keypad) 5 (keypad)
Page 484 Page 10.58 KEY CODE CHART Shifted Control Control Caps Lock Down (Yes/No) Shifted Shift Code Code 7 (keypad) 8 (keypad) 9 (keypad) FAST REPEAT CAPS LOCK SHIFT (right) CTRL SHIFT (left) RESET (NC) (NC) Resets Resets Computer Computer...
Page 485: Keypad Code Chart
Page i0.59 KEYPAD CODE CHART Keypad Codes {key expansion enabled) MODES Normal Alternate Alternate Key(sj Normal Pressed: Unshifted Shifted Unshifted Shifted ENTER ENTER ESC? M ENTER ENTER ESC? n ESC? m ESC? p ESCL ESC? q ESC L ESCB ESC? r ESCB ESC M ESCM...
Page 486: Function Key Code Chart
Page 10.60 FUNCTION KEY CODE CHART Function Key Codes (key expansion enabled) Unshifted Shifted ESC J ESC E ESC S ESC1 A ESC T ESC1 B ESC U ESC1 C ESC V ESC1D ESC W ESC1 E ESC P ESC1 F ESC Q ESC1 G ESC R...
Page 487 Page 11.1 Index Chassis, 9.1 Chassis, cabinet, 8 cables, 9.1 Address/Data circuits, 2.65 Cable location/description, 9.12 Address latches, 2.66 Circuit boards, & hardware, 9.17 Data latches, 2.67 Replacement Parts List, 9.2 Extended addressing, 2.69 All-ln-One, 9.2 General, 2.65 Low profile, 9.8 Circuit descriptions, Address Multiplexer, 2.50 Main board, 2.23...
Page 488: Definitions
Page 11.2 INDEX Disassembly, 1.5 Floppy disk controller, 6.1 Display/Front panel assembly, 1.5 Address lines, 6.24 Keyboard, 1.6 Assembly language code, 6.16 Keyboard shell, 1.6 Bus interface, 6.21 Power supply, 1.7 Calibration, 6.35 S-100 card cage, 1.7 Card clock speed, 6.3 Video logic circuit board, 1.8 Circuit description, 6.23 Main board, 1.9...
Page 489 Page 11.3 INDEX S-100 bus interface, 6.23 Semiconductor identification, 6.39 Signal definitions, 6.50 Initialization sequence, 10.14 Status port, 6.21 Interconnect pin definitions, Status port bit definitions, 6.10 Main board, 2.137 Theory of operation, 6.21 Keyboard, 2.139 Track formats, 6.11 Light pen, 2.139 Troubleshooting, 6.32 Parallel port, 2.138 Vector interrupt lines, 6.4, 6.24...
Page 490 Page 11.4 INDEX Jumpers, 2.4 Keyboard, 2.75 Keyboard, 2.75 Keyboard encoder, 2.23, 3.1 Encoder, 3.1 Auto repeat, 3.3 Encoder output codes, 3.12 Command summary, 3.6 Functions, 3.2 Event-driven mode, 3.3 General, 2.75 FIFO, 3.3 Layout, 3.19 I/O protocol, 3.4 Matrix, 3.11 Key click, 3.3 8041 pin-out, 2.75 Power configuration, 3.3...
Page 491 Page 11.5 INDEX Timer, 2.78 Programming Information, 2.6 DIP switch port (FF), 2.8 Wait timing, 2.44 X-Ray Views, 2.137 High address latch (FD), 2.10 Master 8259A, 2.15 Interrupt 8259A (FO-F3), 2.15 Memory circuit waveforms, 2.53 Light pen port, 2.17 Memory mapping, 10.6 Memory control latch port (FC), 2.11 Parallel port 68A21 (EO-E3), 2.16 Modes of operation, 10.46...
Page 492 Page 11.6 INDEX Slave 8259A, 2.15 Video logic board, 1.4, 4.1 Specifications, Black level control, 4.4 Power supply, 8.3 Circuit Description, 4.48 System monitor ROM, 2.63 CPU-video communications, 4.57 Addressing, 2. 63 Light pen circuits, 4.68 Phantom line, 2.64 Relative memory locations, 4.51 Timing, 4.65 Video arbitration, 4.66 Video output, 4.55...
Page 493 Page 1 1 .7 INDEX Wait state, 2.44 Wait control, 5.6 Width control, 2.44 X-Ray views, Floppy disk controller board, 6.49 Main board, 2.136 Video deflection board, 5.11 Video logic board, 4.106 Z-DOS drive mapping, 10.21 Z-DOS initialization sequence, 10.14...

Zenith Z-100 Series Technical Manual

Chapter 1 General Information

Chapter 3 Keyboard Encoder Description

Chapter 4 Video Logic Board Description

Chapter 5

Chapter 6 Floppy Disk Controller Description

Chapter 7

Chapter 8 Power Supply Power Line Considerations

Power Supply

Chapter 9

Chapter 2

Chapter 10 Description General Information

Quick Links

Troubleshooting

Related Manuals for Zenith Z-100 Series

Summary of Contents for Zenith Z-100 Series

Table of Contents