1. Manuals
  2. Brands
  3. Zenith Manuals
  4. Desktop
  5. Z-100 Series
  6. Reference manual

Zenith Z-100 Reference Manual

Hide thumbs Also See for Z-100:
Table of Contents

Advertisement

Quick Links

Download this manual See also: Technical Manual, User Manual
P rogramm e r'
s

Reference Manual

I I '
data
systems

Advertisement

Table of Contents
loading

Related Manuals for Zenith Z-100

Summary of Contents for Zenith Z-100

  • Page 1: Reference Manual

    P rogramm e r' Reference Manual I I ' data systems...
  • Page 2 P rogramm e r' Reference Manual Z-100 PC Series Computers fAPIFH d a t a systems...
  • Page 3 LIMITED RIGHTS LEGEND Contractor is Zenith Data Systems Corporation of St. Joseph, Michigan 49085. The entire document is subject to Limited Rights data provisions. Trademarks and Copyrights Zenith is a registered trademark of Zenith Electronics Corporation. Z-100 and Z-DOS are trademarks o( Zenith Data Systems Corporation.

  • Page 4: Table Of Contents

    Contents Figures Tables Abbreviations Chapter I Introduction and Specilications Introduction ....Specifications Chapter 2 System Operating Features Introduction ..2.1 Monitor ROM Power-Up Checks . Error Messages.
  • Page 5 Page Iv Contents Number of Floppy Drives ..4.5 Memory Size Autoboot from Selected Drive Monitor Sync Frequency . Programming CPU Functions . S ystem Functions.........
  • Page 6 Page v Contents CRT Controller Mode Select and Status Registers Display Buffer Monitor RAM Character Generator . Timing Generator . Video Output Modes of Operation Text Mode Text Mode Display Architecture 7.10 Graphics Mode 7.11 Medium Resolution (320 x 200) Graphics High Resolution (640 x 200) Graphics 7.14 Programming Video Graphics...

  • Page 7: Introduction

    Page Vl Contents Fundion Code 15 — Return Current Video State 7.39 Function Code 100 — Select Scroging Mode 7.39 Custom Character Creation 7.40 Early Video Cards 7.42 Character Font Selection 7.42 Light Pen Polarity 7.42 Monitor Synchronization 7.43 Chapter 8 Serial an d Parallel Input/Output Introduction .
  • Page 8 Page Vll Contents Figures System Block Diagram ... 3.2 CPU Card Component locations ..4.2 DIP Switch SWI Setlings ... 4.3 DIP Switch SW2 Settings ... 4.5 Alphabetic Keys ..5.4 Nonalphabetic Keys ... 5.6 C ommon Control Keys ......
  • Page 9 Page Viii Contents Tables „0 2.1 Possible Power-Up Diagnostic Messages and Explanations . 2.2 F lag Register Messages . 2.12 2.3 V i deo Mode Selection . 2.14 2.4 Scroll Mode Selection . 2.15 2.5 Special Keys 2.16 2.6 System Memory Map ..
  • Page 10 Page iX Contents 7.19 C haracter Font Selection — Early Video Cards ... 7.42 Parallel Port Address Selection . 8.2 Parallel Map Format . . 8.4 Serial Map Format . 8.4 Serial Byte ¹I Br eakdown. .
  • Page 12 Abbreviations Address Enable American Standard Code for Information Interchange ASCII Basic Input Output System BIOS Carrier Detect Central Processing Unit Cathode Ray Tube Cydic Redundancy Check Clear to Send Dual I nline Package Direct Memory Access Disk Operating System Data Set Ready Error Correction Code Integrated Circuit Input/Output...

  • Page 14: Introduction

    Introduction This manual is designed with the programmer in mind. It contains useful informa- tion about the Z-100~ PC series of IBM PC XT-compatible Zenith Data Systems Computers. Here you will find information about the hardware in these computers and how to use the system Read-Only Memory (ROM) to gain the best performance in your machine and assembly language programs.

  • Page 15: Specifications

    Page 1.2 Introduction and Specifications Specifications Computer Dimensions Z-150 15.75 x 6.25 x 16.5inches(40.0 x 15.9 x 41.9cm) Z-160 19.88 x 8,5 x 19.5 inches (50.5 x 21.6 x 49.5 cm) 62-pin, 8-slot, .825-inch separation, IBM PC XT bus compatible Keyboard 84 ke y s with extended function capabilities, 8048 keyboard pro- cessor...
  • Page 16 Page 1.3 Introduction and Specifications Text 80 characters x 25 lines or 40 characters x 25 lines, soft- ware selectable. G raphics: point addressable 640 x 200 pixels or 320 x 2 0 0 pixels, software selectable. Eight colors, two intensities for RGB output or 16-level gray scale for monochrome output.
  • Page 18 Chapter 2 System Operating Features Introduction This chapter contains information concerning the built-in features of your computer with emphasis on those which will be of primary use in programming the various features and functions. Among the items covered are the following: Monitor ROM System Memory and I/O Address Maps Interrupt Vectors...

  • Page 19: Monitor Rom

    Refer to the Configuration section in Chapter 4 for DIP switch setup instructions. NOTE: Also available is the Disk-Based Diagnostics for the Z-100 PC Series, Model CB-5063-13, a highly comprehensive system checkout and servicing utility. Details on the use of this utility are provided with the Disk-Based Diagnostics package.

  • Page 20: Error Messages

    Page 2.3 System Operating Features Error Messages Table 2.1 describes possible screen error messages that may occur at powerup and what you can check to correct the problem. If your action does not resolve the problem, you will need to have your computer serviced by a qualified indi- vidual.
  • Page 21 Page 2.4 System Operating Features Table 2.1 (continued). Possible Power-Up Diagnostic Messages and Explanations + + + ERROR: I nvalid/No ke yboard code re cei ved! A message of this type indicates that the keyboard did not send the proper code at powerup to indicate proper functioning.

  • Page 22: User-Selected Tests

    Page 2.5 System Operating Features User-Selected Tests In addition to the automatic checks, you may select test sequences from a menu to check the following devices and parameters: Disk drives Keyboard Memory Power-Up status These tests will produce a display that shows you the test name, number of passes made, and keyboard key sequence required to manually end the test.
  • Page 23 Page 2.6 System Operating Features After a test is selected a second screen appears, with the test name at the top of the screen and the message TYPE <ESC> TO ABORT in the bottom left comer of the screen. The test count is displayed in the center of the screen. To end the test, press the ESC key.

  • Page 24: Monitor Rom Routines

    page 2.7 System Operating Features Monitor ROM Routines Another feature of your computer is the collection of monitor ROM routines. While these routines are primarily designed for use in writing, testing, and debugging machine language programs, some of the commands and features can provide an efficient means of locating hardware problems.
  • Page 25 Page 2.8 System Operating Features Command: Help Syntax: ? Purpose: Displays a list of commands and syntax diagrams. Command: Boot from disk SyrttaX: B[drive type] [drive number] [ipnrti tion] Purpose: Reads the operating system boot code from disk and executes it. If an error is detected an error message is displayed.
  • Page 26 Page 2.9 System Operating Features Example: D3313; 0, 13E RETURN In this example, the screen will display the contents starling at memory address 33120H and ending at address 3325EH. Command: Examine memory Syntax: Eaddress address value. -~ Innmber value.-~ Innmber... Purpose: Examines and/or changes the contents of a memory location.
  • Page 27 Page 2.10 System Operating Features Command: Execute (Go) reakpoi n t]. Syntax: G[ =addressl [b Purpose: Initiates program execution with up to eight breakpoints. When a break- point is encountered, the routine saves the processor status for the R and G commands and displays the microprocessor register contents.
  • Page 28 Page 2.11 System Operating Features Command: Move memory block Syntax: Mrauge, address Purpose: Moves the block of memory speciTied by range to the destination, address. The move is implemented in a fashion which prevents overlapping moves from writing over other data. Example: M3219: FEDC, FFFF, 3905: 0 lETURIV In this example, the computer will move 124H bytes of data from 4206CH to 39050H.

  • Page 29: F Lag Register Messages

    Page 2.12 System Operating Features The FL (flags) register contents are not displayed in hexadecimal, but as a two-letter abbreviation representing the specific flag's condition as defined in Table 2.2. Table 2.2. Flag Register Messages FIAG Overflow OV ( o verflow) (no overflow) Direction DN (down)
  • Page 30 Page 2.13 System Operating Features Command: Trace program Syntax: T[=address] [, value] Purpose: Traces a user program. Single steps through the program beginning at address, displaying the microprocessor register contents a' each instruction is executed. The value determines how many times to execute before returning control to the user.

  • Page 31: V I Deo Mode Selection

    Syntax: V [Mvi d eo otode] [Sscroll mode] [100[ [150[ Purpose: This command is used to set the current video mode or scroll mode. Use 100 or 150 to determine which hardware mode to use (100 signifies Z-100 bit-mapped graphics with Z-319 bit-mapped video graphics accessory, 150 signifies IBM PC-compatible graphics).

  • Page 32: Scroll Mode Selection

    Page 2.15 System Operating Features Table 2.4 indicates the scroll modes obtainable with the VS command. The scroll mode determines the manner in which information on the screen is handled once the screen is full. Table 2.4. Scroll Mode Selection CODE SCRO L L MODE Software compatible scroll mode.

  • Page 33: Special Keys

    Page 2.16 System Operating Features Special Keys Table 2.5 defines the keyboard keys and associated functions recognized by the ROM diagnostics. These keys permit certain editing operations and control the format of the screen display. Table 2.5. Special Keys FUNCrlON BACK SPACE Press to correct typographical errors prior to com- mand line execution.

  • Page 34: System Memory And I/O Address Maps

    Page 2.17 System Operating Features System Memory and I/O Address Maps This section shows the memory layout scheme of your computer and the locations of the I/O ports. Table 2.6 is a general memory breakdown of the system. Table 2.6. System Memory Map HEXDECI MAL DECIMAL ADDRESS ADDRESS...

  • Page 35: I / O Port Addresses

    Page 2.18 System Operating Features Table 2.7 indicates the I/O port addresses and the respective device assignments. For further breakdowns of the individual device I/O ports, refer to the chapter that covers the specific device. Table 2.7. I/O Port Addresses HEXADECIMAL ADDRESS RANGE DEVICE 000-OOF...

  • Page 36: Interrupt Vectors

    Page 2.19 System Operating Features Interrupt Vectors The interrupt vectors recognized by the microprocessor in your computer allow the different devices on the I/O bus to halt CPU operation when an operation related to the device requires service. Table 2.8 lists the interrupt vectors which may occur as the result of various assembly level programming operations.

  • Page 37: Special Interrupt Vectors

    Page 2.20 System Operating Features Table 2.10 lists the Basic Input/Output System (BIOS) entry point interrupts. Table 2.10. BIOS Entry Point Interrupts VECTOR FUNC T ION Video I/O Determine I/O configuration Determine memory size Disk I/O Serial I/O (RS-232 I/O) Not used Keyboard I/O Printer I/O...

  • Page 38: Support Packages

    You may also be interested in the optional plug-in cards, and the various program- ming languages, applications, and utility packages, available for your computer from Zenith Data Systems. These options include detailed implementation of many of the programming features of your system. Contact your Zenith Data Systems dealer for details on these packages.

  • Page 40: System Input/Output

    Chapter 3 System Input/Output Introduction This chapter describes the manner in which information is passed between the different elements that make up the computer system. The information contained in this chapter is intended as a general overview of the system only. It provides preparatory material for the chapters which follow and contains specific programming information and data for the various functions and features available in your system.

  • Page 41: System Layout

    Page 3.2 System Input/Output System Layout Figure 3.1 shows the overall block diagram of the system. F LOPPY D I S K W INCHEST E R DRIVE DRIVE(S) POWER WINCHES TE R F LOPPY D I S K SI/PPLY DRIVE C ONTROLL E R CONTROLLER K EYBOAR D...

  • Page 42: System Bus Board

    Page 3.3 System Input/Output As you can see, the main artery for system communication is the I/O bus, which acts as the main trunk for information transfer. What is not readily apparent from the block diagram, is that the CPU acts as the main traffic control element for information flow.

  • Page 43: System Bus Signal Names

    page 3.4 System Input/Output Connection to the bus by the cards in the system is also made through the edge connectors on the backplane board. Each of the standard cards, and any custom add-on cards, interface with the CPU through one of these connectors. This chapter will be limited to defining the signals which appear on the electrically parallel pins of these connectors.
  • Page 44 Page 3.5 System Input/Output Table 3.1(continued). System Bus Signal Names SIGNAL DEFINITION Address bit 7 Address bit 6 Address bit 5 Address bit 4 Address bit 3 Address bit 2 Address bit I Address bit 0 Ground RESET When high, resets or initializes system logic devices. +5 VDC + 5 VDC bus.
  • Page 45 Page 3.6 System Input/Output Table 3.1 (continued). System Bus Signal Names P IN SIG N A L DEFINITION B 19 DAC K O DMA acknowledge 0. Assigned to timer ¹1. Initiates memory refresh cyde. System clock 4.77 MHz. IRQ 7 Interrupt request 7.

  • Page 46: Central Processing Unit

    Chapter 4 Central Processing Unit Introduction The CPU in your computer contains an 8088 microprocessor, DMA and interrupt processing circuitry, system clock, and timing and control generation circuitry. From a programming standpoint, the CPU functions are largely accessed through the built-in ROM routines, or by means of iAPX 88 assembly level instructions. The instruction set and programming information for the 8088 microprocessor are detailed in the iAPX 88 Book included in this package, and will not be repeated here.

  • Page 47: Dip Switches

    pay. 4.2 Central Processing Unit Configuration Configuration of the hardware features and options in your system is selected by DIP switches SW1 and SW2 and by jumper block P203. P203 is a ROM size select jumper block, which is set at the factory, and should not require changing. DIP Switches Refer to Figure 4.1 for the location of SW1 and SW2, the two 8-section DIP switch packages.
  • Page 48 Page 4.3 Central Processing Unit Figure 4.2 shows SW1 set for a typical system configuration. Refer to Table 4.1 for the proper switch settings for your system. F LOPPY D R I VE S A T T A C H E D ? 8 087 C O P R O C ES S O R I N S T A L L E D ? OF CARD B ASE SIZE OF M E M O R Y...

  • Page 49: Floppy Drives Present

    Page 4.4 Central Processing Unit Table 4.1. Dip Switch SWl Settings SECTION AND SElTING FUNCTION CONFI G URATION Floppy Disk one or more Right Drives none installed Left 8087 not installed Right Coprocessor Left Left Memory device other options reserved base size Right Left...

  • Page 50: Memory Device Base Size

    Page 4.5 Central Processing Unit Memory Device Base Size Sections 2 and 3 of SW1 indicate the base memory device size. 64K is the only presently acceptable option. Sections 2 and 3 are both positioned to the left; any other combinations are reserved. Monitor Line Length Sections 4 and 5 of SW1 define the monitor line length, in characters, when the computer is turned on.

  • Page 51: Memory Size

    Page 4.6 Central Processing Unit Table 4.2. DIP Switch SW2 Settings FUNCTION CONFIGURATION P O SITION AND SETTING R ight R i g h t 128K R ight L e f t Right R ight R i g h t 192K R ight R i g ht...

  • Page 52: Monitor Sync Frequency

    Page 4.7 Central Processing Unit Monitor Sync Frequency Section 7 of SW2 tells the CPU at what vertical sync frequency the monitor should run. Select the position that corresponds to your AC power line frequency. Nor- mally, this will be 60 Hz in North America.

  • Page 53: S Ystem Functions

    Page 4.8 Central Processing Unit Programming CPU Functions The portion of this manual on programming the CPU operations will, of necessity, be brief. The operations are largely "housekeeping" types of routines. Also included are functions which cannot be otherwise put into the other sections. Induded here are system functions which will print screen routines, determine I/O configuration, determine memory size, and set and read the time-of-day.
  • Page 54 Page 4.9 Central Processing Unit Table 4.3. VO Configuration Data BIT ¹ MEANING Disk drives installed in system. 8087 coprocessor i ns t al l ed. Amount of base RAM (device size) installed on the user memory card(s). 4 & 5 Initial video mode Unused 40 x 25 Monochrome on the color card.

  • Page 55: Interrupt 12H — Determine Memory Size

    F000:FFFO — Power-up reset vector. F000:FFED — Jump unconditionally to the MFM-150 monitor/debugger. F000:FFEA — Set machine mode if AL = OFFH, Z-100 mode will be en- tered using the Z-319 Bit-Mapped Video Graphics Card. If AL = 0, Z-150 mode will be entered using the Z-309 Video...

  • Page 56: Sound Programming

    Page 4.11 Central Processing Unit Sound Programming Sound may be programmed in one of three different ways: • Puls e train generated by toggling a program control register bit • The o u t put of Channel 2 of the timer/counter programmed to deliver a sound waveform to the speaker •...

  • Page 58: Chapter 5 Keyboard Introduction

    Chapter 5 Keyboard Introduction The keyboard entry point permits an application program to determine the status of the keyboard or to receive characters entered through the keyboard.

  • Page 59: Interrupt 16H — Keyboard Input/Output

    Page 5.2 Keyboard Interrupt 16H — Keyboard Input/Output Three operation codes are used with this interrupt to determine the function to be performed. 0 — Get a character from the keyboard 1 — Determine if a key code is waiting in the keyboard's buffer 2 —...

  • Page 60: Responses To Interrupt 16H

    page 5.3 Keyboard Table 5.1. Responses to Interrupt 16H OPERATION CODE CONDITION RESPONSE Character Entered ASCII code will be in register AL. Scan code will be in register AH. C haracter i s r e moved f r o m the keyboard buffer.

  • Page 61: Keyboard Configuration

    Page 5.4 Keyboard Keyboard Configuration This section repeats much of the information found in the User's Guide and Operaffons Manual. It describes the various groups of the keyboard, how they are typically used in software applications, and the codes produced by each key undervarious conditions.

  • Page 62: A L Phabetic Key Scan Codes

    Page 5.5 Keyboard The scan codes generated from the alphabetic keys are listed in Table 5.2. The least-significant byte of the scan code is the value returned as the ASCII code. Table 5.2. Alphabetic Key Scan Codes (SHIFT) (CTRL) (ALT) CAPS LOCK SHIFTED SHIFTED...

  • Page 63: Nonalphabetic Keys

    Page 5.6 Keyboard The nonalphabetic keys, identified in Figure 5.2, include the numbers 0 through 9, the common punctuation marks, and the special programming characters that make up the remainder of the printing ASCII character set. Since each of these keys has one character, the upper character is generated by pressing either SHIFT key.

  • Page 64: N O Nalphabetic Key Scan Codes

    Page 5.7 Keyboard Table 5.3. Nonalphabetic Key Scan Codes (SHIFT) (CTRL) (ALT) SHIFTED SHIFTED CONTROL ALTERNATE 0231H 0221H 7800H 0332H 0340H 0300H 7900H 0433H 0423H 7AOOH 0534H 0524H 7BOOH 0635H 0625H 7COOH 0736H 075EH 071EH 7DOOH 0837H 0826H 7EOOH 0938H 092AH 7FOOH OA39H...
  • Page 65 Page 5.8 Keyboard Table 5.3 (continued). Nonalphabetic Key Scan Codes (SHIFT) (CTR L ) (ALT) SHIFTED CON T RO L ALT E RNATE SHIFTED 2822H 2827H 332CH 333CH 343EH 342EH 352FH 353FH 2B7CH 2BlCH 2B5CH...

  • Page 66: C Ommon Control Keys

    Page 5.9 Keyboard The common control keys are shown in Figure 5.3; the scan codes and the usual software function are listed in Table 5.4. • j. • " 8, „ ) --- oo Fj j Figure 5.3. Common Control Keys...
  • Page 67 page 5.10 Keyboard cn cn 9 =„2 C 0 0 O O d' a > j='i L cj j cjoy ) c j j «f) 0 c/J Q ~o x «D x cD «D «D «x3 «D x cD «D «D...
  • Page 68 Page 5.11 Keyboard The special function keys are identified in Figure 5.4. The scan codes and usual function (if any) are listed in Table 5.5. Note that the keypad special functions are shown in this figure and table, along with the codes for the numeric function, although they are not specifically called out in the Usual Function column.
  • Page 69 page 5.12 Keyboard OJ M C A CO C QO C F ) o g ~ a) ~ a 0 c o c a c 0 c . a a .a a .a a a a a g I/> 0 a>...
  • Page 70 Page 5.13 Keyboard...
  • Page 71 page 5.14 Keyboard o o o 4> 4,9p o o ~ x C O x <D x C) C>...
  • Page 72 Page 5.15 Keyboard...

  • Page 73: Control Keys

    Page 5.16 Keyboard The control keys are identified in Figure 5.5. The ALT and CTRL keys do not generate a code but modify the codes of the other keys. The ESC key generates ASCII code IBH (Scan code OIIBH). The ESC function is often used by software to stop the execution of a program or, when used in sequence with another key, as a means of entering escape codes required by some software.

  • Page 74: Keypad Special Keys

    Page 5.17 Keyboard The minus key (-) produces the scan code 4A2DH and the plus key (+ ) produces 4E2BH. The ENTER key produces the same scan codes as the RETURN key' (1CODH in the shifted and unshifted modes and 1COAH when used with the CIRL key) and is usually used in the same way.

  • Page 75: Increasing Keyboard Buffer Size

    ROM. Several of the instructions must be carried out before any input from the keyboard will be properly recognized. Therefore, you must use an assembler, such as the Microsoft Macro Assembler, available as part of the Programmer's Utility Pack from Zenith Data Systems.
  • Page 76 Page 5.19 Keyboard The following assembly language example sets put aside the top SK of unused Z-100 PC monitor RAM as a 4K character keyboard buffer. MONITOILSEGMENT SEGMENT AT (OFOOOH) ;2-100 PC mo nitor data segment KEYMUFFDEGMENT EQU OCSH ;Buffer se gm ent...
  • Page 77 Page 5.20 Keyboard To compile the above code using the Macro assembler, enter the following com- mands: MASM BI G KBUFF; LINK BIGKBUFF; EXE2BIN BIGKBUFF. EXE . CO M The MASM file is only on the Programmer's Utility Pack distribution disk. The LINK and EXE2BIN files are both on the second distribution disk of MS-DOS.

  • Page 78: System Memory

    Chapter 6 System Memory Introduction This chapter contains information and descriptive material related to programming operations as they apply to the system memory (RAM) banks. Refer to the information in Chapter 2 under ROM Diagnostics which applies to memory access and manipulation, specifically the Enter, Go, Move, Search, and Unassemble commands.

  • Page 79: General

    page 6.2 System Memory General The memory cards contain the main user-accessible dynamic RAM and associated timing and multiplexing circuitry. These cards interface with the system through one of the parallel I/O connectors located on the backplane board. Connection with the cards is implemented through the use of a 64-pin edge connector which is an integral part of the cards.

  • Page 80: Dip Switches

    Page 6.3 System Memory The RAM ICs feature on-chip refresh which is initiated when a given address is read. The card also provides the necessary circuitry to control wholesale refresh at required intervals, to arbitrate read, write, or refresh requests, and to properly time the various memory access operations.
  • Page 81 Page 6.4 System Memoly MEMORY CARD Figure 6.1. Memory Canl Select Jumper locations...

  • Page 82: Theory Of Operation

    Page 6.5 System Memory Theory of Operation In order to darify exactly how memory is accessed and manipulated, the following description of memory circuit operation is provided. Refer to the memory card block diagram in Figure 6.2 for the general functional description of the memory circuits which follows.

  • Page 83: Memory Access Operations

    Page 6.6 System Memory Memory Access Operations A memory access cyde may be initiated by one of three requests: memory read, memory write, or refresh. The Address Enable Signal (AEN) must also be active for any of these requests to initiate access. Contention between these requests, timing, and row and column address selection, is handled by the address logic.
  • Page 84 Page 6.7 System Memofy The ninth memory address bit, MA8, connects to pin 1 on each of the RAM sockets. Since pin I has no internal connection on 6665 or 4164 ICs, MA8 is only used when 256 kilobit chips are installed. The heart of the memory card is the memory itself.

  • Page 85: Data Buffer

    Page 6.8 System Memory Table 6.1 graphically illustrates the bank select logic. Table 6.1. RAM Bank Select Logic FIR S T A 1 9 A 1 8 A17 A16 R A STIM M EMORY RANGE B ANK First Block (Card 1) 000 0 0-OFFFF 1 00 0 0-IFFFF 200 0 0 -2FFFF...

  • Page 86: Parity Generation And Error Detection

    Page 6.9 System Memory Parity Generation and Error Detection When a write operation is being processed, the parity generator looks at the 8-bit data word and determines if an odd number of logical ones (Is) are present or not. If not, the parity generator places a logical I in the corresponding memory location of the parity RAM chip of the bank where that piece of data resides.

  • Page 87: System Memory Map

    Page 6.10 System Memory System Memory Map Table 6.2 shows the location of user memory in the system memory scheme. Table 6.2. System Memory Map HEXADECIMAL DECIMAL ADDRESS ADDRESS TYPE OF MEMORY 0000000-0327679 00000-4FFFF 1st RAM Card 0327680-0655359 50000-9FFFF 2nd RAM Card 0655360-0720895 A0000-AFFFF Reserved...

  • Page 88: Programming User Memory

    Page 6.11 System Memory Programming User Memory In general, programming user memory is very simple and straightforward. Most of the access operations can be performed directly from the built-in ROM routines or from assembly level programs written using the Programmer's Utility Pack Typical memory access operations indude: Reading and writing to specific memory locations Allocating specific sections of memory to dedicated purposes, such as often...

  • Page 89: Disabling The Parity Circuits

    Page 6.12 System Memory For example, the value 3F3F:5B11 would represent memory address 44F01 hexadecimal (282369 dedmal), since 3F3F shifted left equals 3F3FO (259056 deci- mal) plus 5B11 (23313 decimal) equals 44F01H. Since the least-significant digit of the segment is always 0, it should be apparent that more than one combination of segment and offset can point to the same memory address.
  • Page 90 Chapter 7 Video Graphics Programming Introduction This chapter provides hardware and software programming information for the video card in your Z-100 PC Series Computer. Among the features covered are: Character font and monitor synchronization selection Text mode programming Medium and high resolution graphics...

  • Page 91: Configuration Jumpers

    page 7.2 Video Graphics Programming The following are features, functions, and capabilities of the video card: Addressing, reading, and writing to the 16K video RAM with no timing restric- tions or display interference Foreground, background, and border color selection Text mode or pixel addressable graphics mode selection Selection of one of four built-in 256-character ROM fonts Up to 128 user-defined characters 7 or 14 MHz video bandwidth, mode dependent...
  • Page 92 Page 7.3 Video Graphics Programming • A • • VIDEO CARD VIDEO CARD Figure 7.1. Video Card Jumper Incations...

  • Page 93: Power-Up Character Font Selection

    J301, the light pen jumper, to "+". If your pen outputs a negative-going pulse, position J301 to "— ". The light pen option currently is not supported by Zenith Data Systems. Character Font Selection Figure 7.2 depicts the contents of the character font ROM, and the ASCII hexadeci-...

  • Page 94: C Haracter Rom Contents

    Page 7.5 Video Graphics Programming Figure 7.2. Character ROM Contents...
  • Page 95 RGB monitor, positive "+ " or negative " — ". NOTE: The jumpers are set at the factory for most Zenith Data Systems monitors. The jumpers J303 and J306 in the Z-160 models are properly set at the factory for the internal monitor's electronics so you shouldn't have to change these two jumpers.

  • Page 96: Crt Controller

    Page ?.? Video Graphics Programming Major Components The videod rcuitry is comprised of the following major components. CRT Controller A 6845 CRT controller IC provides the proper drive signals for a raster scan CRT. The device is highly programmable with regard to raster and character manip- ulation, and allows for the implementation of many display modes.

  • Page 97: Character Generator

    Page 7.8 Video Graphics Programming Character Generator The ROM character generator on the video card, when in text mode, generates software-selectable characters from dot p atterns stored in the ROM. Four character configurations are provided: 7 x 7 double-dot width, 5 x 7 single-dot width, and underlined versions of either of these character sets.

  • Page 98: Modes Of Operation

    Page 7.9 Video Graphics Programming Modes of Operation The video card can operate in one of two major modes: text mode and pixel addressable graphics mode. Additional submodes are available within each mode, for either color or monochrome display. Text Mode In text mode, the display formats in either a 40-column by 25-line submode, or in an 80-column by 25-line submode.

  • Page 99: Text Mode Display Architecture

    Page ?.10 Video Graphics Programming Text Mode Display Architecture A 2-byte character and attribute format is used to define each character display position as shown in Figure 7.3. A ttr i b ut e B y t e ( M+t ) C harac te r B y t e ( M ) Figure 7.3.

  • Page 100: Graphics Mode

    Page 7.11 Video Graphics Programming Table 7.3 shows the attribute byte breakdown. As before, bits 7 and 3 determine blink and intensity, respectively, of the foreground character. Table 7.3. Color Attribute Byte Logic BACKGROUND BITS FOREGROUND BITS COLOR Black Blue Green Cyan Magenta...

  • Page 101: Graphics Storage Map

    Page 7.12 Video Graphics Programming Medium Resolution (320 x 200) Graphics Pixel information is stored in video memory in two banks of 8000 bytes each, as shown in Figure 7.4. Address B8000 contains color selection data for the pixels in the upper left corner of the display area. Addresses B8000 to B9F3F contain information for pixels in even numbered rows 0 through 198.

  • Page 102: C O Lor Select Logic

    Page 7.13 Video Graphics Programming For a given pixel bit pair composed of bits CO and Cl, the following logic, as shown in Tables 7.4 and 7.5, determines which color is selected from one of four colors: the current background color or one of the three colors from the current palette.

  • Page 103: High Resolution Mapping

    Page 7.14 Video Graphics Programming High Resolution (640 x 200) Graphics The high resolution (640 x 200) graphics submode may only be implemented in a monochrome format because of memory limitations. Addressing and mapping is the same as medium (320 x 200) resolution but formatting of the data is different In this submode each bit, as opposed to a bit pair.

  • Page 104: Crt Controller Signals

    Page 7.15 Video Graphics Programming Prograauning Video Graphics In the following descriptions all address and register values are given in hexadeci- mal notation. The term "set" in a given bit position indicates a logic I state. The term "reset" indicates a logic 0. The memory used by the video interface is a self-contained 16 kilobyte bank with no parity bit.

  • Page 105: V I Deo Card To System Interface Signals

    Page 7.16 Video Graphics Programming Table 7.6. Video Card to System Interface Signals SIGNAL NAME DESCRIPTION AO to AI9 The 20 system address lines used to access memory locations. DO to D7 Bidirectional data lines which transfer information between the CPU and the internal registers of the 6845.
  • Page 106 page 7.17 Video Graphics Programming Table?.6. (continued) Video Card to System Interface Signals SIGNAL NAME DESCRIPTION Enables the internal VO buffers and docks data into and out of the internal registers via the data buffers. In your computer, the E input connects to the system ECLK signal. Synchronizes the 6845's control signals.

  • Page 107: Screen Memory And Character Generator Signals

    page 7.18 Video Graphics Programming Screen Memory and Character Generator Si gnals There are two sets of signals provided by the 6845 to implement screen memory and character generator logic interface. MAO through MA13 are screen memory address outputs and RAO through RA4 are the raster address signals sent to the character generator logic.

  • Page 108: Programming The Registers

    Page 7.19 Video Graphics Programming The other eighteen registers are selected by the pointer information in the address register. Then the CPU directs the information at address 3DS to be loaded into the selected register. Transfers of address and parameter information to and from the registers is via data lines DO through D7.
  • Page 109 Page 7.20 Video Graphics Programming x ~~ ccrc 8 0 C 0 N 0 0 N M 8 g,5 Q 0 0...
  • Page 110 Page 7.21 Video Graphics Programming...
  • Page 111 page 7.22 Video Graphics Programming...

  • Page 112: Horizontal Timing And Format Registers

    Page 7.23 Video Graphics Programming The first group of registers, RO through R3, establishes the horizontal format and timing parameters. Registers R4 through R9 determine vertical format and timing parameters. The remaining registers, R10 through R17, deal with cursor characteristics, screen memory addressing, and the light pen interface.

  • Page 113: Vertical Timing And Format Registers

    Page 7.24 Video Graphics Programming Vertical Timing and Format Registers Registers R4 through R9 are normally loaded at system startup and are not nor- mally changed later. The point of reference for these registers is the top-most character position displayed on the monitor screen. The vertical total register, R4, and the vertical sync adjust register determine the total number of scan line times in a frame, induding vertical retrace, establishing the overall frame rate or VSYNC frequency.

  • Page 114: P Rimary Operating Registers

    Page 7.25 Video Graphics Programming The scan line spedfied in RIO is the first scan in which the CURSOR signal is to be set and it will remain set until the scan line specified in Rll has been completed. Accordingly, if you want the cursor symbol to occupy a single scan line, the same value must be loaded into both registers.

  • Page 115: Raster Scan Signals

    Page 7.26 Video Graphics Programming Raster Scan Signals The raster scan outputs, RAO through RA4, provide the interface between the 6845 and the character generator logic. These outputs may represent scan line counts of from 0 to 31, or up to 32 scan lines per character row. Register R9, the scan lines/row register, determines the maximum count from the scan output registers before reset occurs.

  • Page 116: Video Card Input/Output Devices

    page 7.27 Video Graphics Programming Video Card Input/Output Devices Table 7.8 defines the I/O registers contained on the video interface and the port assignments. Table 7.8. Video Card Input/Output Port Assignments PORT ADDRESS R E GISTER 6845 6845 Mode Control Color Select Status/Mode Input/Output Light Pen Latch CLEAR...

  • Page 117: Color Select Register

    page 7.28 Video Graphics Programming Color Select Register The color select register, located at address 3D9, is a 6-bit output only device (it cannot be read) that can be written to using the I/O OUT command. Only the six LSBs of the instruction are used, as shown in Table 7.10. Tabk 7.10.

  • Page 118: Mode Select Registers

    Page 7.29 Video Graphics Programming If bit 5 is a logical 0, color is determined by the logic of Table 7.12. Table?.12. Palette 4 2 Selection Cl C O B A C K G ROUND COLOR Defi n e d by bits 0-3 of port 3D9 Green Brown Mode Select Registers...

  • Page 119: Mode Select Port 3Da Logic

    Page 7.30 Video Graphics Programming The output register at 3DA functions according to the logic of Table 7.14. Table 7.14. Mode Select Port 3DA Logic DESCRIPTION A logical I overrides the VIDEO ENABLE signal from 3D8. Eliminates monitor display flicker when in text mode. Character font selection (see Table 7.15).

  • Page 120: Character Font Selection

    page 7.31 Video Graphics Programming Table 7.15 further defines the manner in which character font selection is deter- mined. Table 7.15. Character Font Selection MODE SELECT STATUS PORT PORT3DA J305 J302 B IT 1 B I T 5 BIT 6 FONT Power-up double-dot Single-dot...

  • Page 121: Status Register

    Page 7.32 Video Graphics Programming Status Register The status register, an 8-bit read only buffer, resides at input port address 3DA. operation o f this register. Table 7.16 summarizes the logical Table 7.16. Status Port 3DA Logic DESCRIPTION Logical I indicates that a horizontal or vertical retrace is in progress. Used to update the video memory during screen refresh intervals.

  • Page 122: Programming Interface Information

    Page 7.33 Video Graphics Programming Programming Interface Information T he information in t his section repeats much of th e f oregoing, but i s arranged in a format designed to darify and link together related concepts and operations. Specific instrudions are presented here, which, together with the previ- ous data, will enable you to perform spedfic programming operations.

  • Page 123: Video Input/Output Function Codes

    Page 7.34 Video Graphics Programming Table 7.17. Video Input/Output Function Codes REGISTERS FUNCTION OPERATION AFFECTED CODE Set screen mode Set cursor type CH, CL Set cursor position DH, DL Read cursor position DH, DL, CH, CL Read light pen position 2 3 4 5 6 7 AH, DH, DL, CH, BH, BL Select active display page...

  • Page 124: Function Code 0 — Set Video Mode

    Page 7.35 Video Graphics Programming Function Code 0 — Set V i deo Mode To set the desired video mode, a value from 0 to 7 is placed in the AL register before implementing the interrupt command. The recognized modes and their function codes are presented in Table 7.18.

  • Page 125: Function Code 3 — Read Cursor Position

    Page 7.36 Video Graphics Programming Function Code 3 — Read Cursor Position Upon return from this call, DH will contain the cursor row, and DL the cursor column position. Function Code 4 — Read Light Pen Position Upon return, AH will contain the light pen trigger/switch status, 0 or 1. If AH is 0, the light pen has either not been triggered, or not been switched active.

  • Page 126: Function Code 7 — Scroll An Area Of The Screen Down

    Page 7.3? Video Graphics Programming Function Code 7 — Scroll an Area of the Screen Down This code allows you to define an area of the screen to be scrolled downward a desired number of lines. Load registers the same as for scrolling up. Function Code 8 —...

  • Page 127: Function Code 12 — Write Graphics Pixel

    page 7.38 Video Graphics Programming If BH is odd, one of the two available palettes is selected by the value in BL. If BL is 0, the green (I), red (2), yellow (3) palette is selected; if BL is I, the cyan (I), magenta (2), white (3) palette is selected.
  • Page 128 Page 7.39 Video Graphics Programming Function Code 15 — Return Current Video State Returns to the current video status. AL will hold the current video mode (function code 0), AH the screen width in character columns, and BH the currently active video page.

  • Page 129: Custom Character Creation

    Page 7.40 Video Graphics Programming Custom Character Creation Normally when in graphics mode, characters called from the computer's ROM are the first 128 characters of the character font In addition to these standard characters, you may create your own 128 custom character set using the following procedure.
  • Page 130 Page 7.41 Video Graphics Programming Proceed in this manner to define each character in your set. When you have all the characters defined and placed in memory, the first character will have a hexadecimal code of 80 and the last a code of FF. All that remains now is to reset the pointer at interrupt vector 1F to the start of the memory section where your characters reside.

  • Page 131: Early Video Cards

    Page 7.42 Video Graphics Programming Early Video Cards If your computer is an early system, it may use a different video card instead of the present design. The two cards are easily distinguished from each other. The early card has seven configuration jumpers instead of eight, and the two connectors which project from the top rear of the present card are installed on the card field on the earlier design.

  • Page 132: Monitor Synchronization

    Page 7.43 Video Graphics Programming Monitor Synchronization If you are using an RGB (color) monitor which requires composite (horizontal and vertical) sync, position J303 to "C". If your monitor requires separate horizontal and vertical sync, position J303 to "V'. Position J305 to the video card markings corresponding to the vertical sync polarity required by your monochrome monitor, positive "+ ", or negative "—...

  • Page 134: Chapter 8 Serial An D Parallel Input/Output Introduction

    Serial and Parallel Input/Output Introduction As with most of the other programmable features of the Z-100 PC Series Com- puters, the easiest and most direct means of manipulating the flow of serial and parallel data to a real world device (usually a printer), is by means of the routines provided in the monitor ROM, built into the machine.

  • Page 135: Configuration

    Page 8.2 Serial and Parallel Input/Output Configuration Configuration hardware jumpers are provided on the floppy disk controller card for the serial I/O ports and on the standard memory card for the parallel interface. Serial Port Configuration Serial port ¹I (C OMI), physically the top connector on the rear of the floppy disk controller card, is configured to interrupt request ¹4 (IR4).

  • Page 136: Serial/Parallel Input/Output Tables

    Page 8.3 Serial and Parallel Input/Output Serial/Parallel Input/Output Tables Figure 8.1 graphically illustrates the format for the serial and parallel device param- eter mapping. PARALLEL DEVICE + 1 R OM ENT R Y PARALLEL FROM D EVICE + 2 INTERRUPT 1 7 H PARALLEL D EVICE + 3 SERIAL...

  • Page 137: Parallel Format

    page 8.4 Serial and Parallel Input/Output Parallel Format The format for each of the three parallel maps is shown in Table 8.2. Table 8.2. Parallel Map Format BYTE PARA M E TER DESCRIPTION Bits 0-3 perform a map Bit 4 strips parity on the output Bit 6 maps l owercase t o uppercase Pad character af t er carr i age r etu rn Number of pad characters to issue...

  • Page 138: Serial Byte ¹2 Breakdown

    Page 8.5 Serial and Parallel Input/Output Table 8.4 further defines byte ¹ I by bit. Table 8.4 Serial Byte ¹1 Breakdown PARAMETER DESCRIPTION Compatibility bit If logic I, IBM-compatible DTR and RTS high. If logic 0, handshake determined by bit l. Protocol bit.

  • Page 139: Serial Byte ¹7 Breakdown

    Page 8.6 Serial and Parallel Input/Output Table 8.6 further defines byte ¹7. Table 8.6. Serial Byte ¹7 Breakdown PARAMETER DESCRIPTION 0&I Word size Number of stop bits Define parity; yes/no odd/even 3 &.4 Baud rate 5,6,&7...

  • Page 140: Interrupts

    Page 8.7 Serial and Parallel Input/Output Interrupts The interrupts recognized by the system for the serial and parallel devices are 17H for the parallel I/O ports and 14H for the serial I/O ports. The following operation codes, when placed in the 8088 AH register, will result in specific actions as defined in the following paragraphs.

  • Page 141: F Unction Code 0 — Initialize The Serial I/O Port

    page 8.8 Serial and Parallel Input/Output Serial Port The following operations are recognized using the serial interrupt, 14H. As before, AH is loaded with the operation code corresponding to the desired function. DX is loaded with the serial device designator, 0 or I, before the interrupt is executed. Table 8.8 defines the operation codes recognized by the system when using the serial interrupt Table 8.8.

  • Page 142: Word Length Selection

    Page 8.9 Serial and Parallel Input/Output Table 8.10. Word Length Selection BIT I BI T 0 W O R D LENGTH Don ' t care Don ' t care 7 bit s 8 bit s Table 8.11. Parity Selection BIT 4 BIT 3 SEL E CTION No parity...

  • Page 143: Function Code 2 — Receive Character From The Serial Port

    Page 8.10 Serial and Parallel Input/Output Function Code 2 — Receive Character from the Serial Port Upon return from this call, bits 7, 4, 3, 2, and I of AH will contain the data transfer status. Again, refer to Function Code 3. If AH is logic 0, the routine reads a character properly into AL lf AH is not 0, some type of error occurred.

  • Page 144: Modem Control Status (Register Al)

    Page 8.11 Serial and Parallel Input/Output Table 8.14. Modem Control Status (Register AL) STATUS CTS line has changed state. DSR status has changed. End of ringing pulse detector. Carrier Detect (CD) signal has changed state. Status of CTS line. Status of DSR line. Ringing indicator.

  • Page 146: Mitsubishi Floppy Disk Drive

    Chapter 9 Disk Drives Introduction This chapter contains hardware and software programming information for the floppy disk drives, Winchester drives, and the drive controller cards. Refer also to the section on the Central Processing Unit for the correct DIP switch settings for the desired system configuration, including: the selection of the auto- boot, drives present, and number of drives option.

  • Page 147: Disk Drives

    9 . 2 Disk Drives Configuration Various configuration jumpers and a switch on the Winchester drive controller are employed on the drive controller and drive signal separator cards to implement optional operational modes. This section will discuss the positioning of those jurn- pers for your particular application.

  • Page 148: Mitsubishi Floppy Disk Drive Configuration

    Page 9.3 Disk Drives Also located on the Winchester controller card is a 4-section switch, Sl, which selects the number of hard disk heads/cylinders in use. Table 9.1 defines the head and cylinder seledion for the section settings. The ON position of a section represents a logic I and OFF represents a logic 0.
  • Page 149 Page 9.4 Disk Drives JUMPER CONFIGURATION DRIVE B DRIVE A TERMINATOR JUMPERS DRIVE C DRIVE D FLAT CABLE POWER CONNECTOR CONNECTOR STRIP P ROGR A M M IN G JUMPERS Figure 9.2. Mitsubishi Floppy Disk Drive Configuration Table 9.2. Mitsubishi Floppy Disk Drive Configuration JUMPER POSITIONS DRIVE DSO D SI...

  • Page 150: Shugart Floppy Disk Drive Configuration

    Page 9.5 Disk Drives Shugart Floppy Disk Drive Configuration If your system is equipped with one or more Shugart floppy disk drives, use this section to configure your system. Refer to Figure 9.3 and Table 9.3 to configure the drive(s) by jumpering the appropriate pins. Remove the terminating resistor pack on all drives except for the last drive on the cable.

  • Page 151: Drive Function Calls

    page 9.8 Disk Drives Drive Function Calls Table 9.6 defines the drive functions recognized by the system. Table 9.6. Drive Functions CODE FUN C TION Reset disk system. Read disk status. Read specified sectors into a buffer. Write buffer contents to desired sectors. Verify that selected sectors can be read without error.

  • Page 152: Drive Parameter

    Page 9.9 Disk Drives Function Code 0 — Reset Disk System This call resets the disk software for each drive in the system. For floppy drives, interrupt vector 1EH should point to a drive parameter block as defined by Table 9.7.

  • Page 153: Function Code 5 — Format Track

    Page 9.10 Disk Drives Table 9.8 defines the parameters required by function codes 2 through 5. Table 9.8. Required Parameters for Function Codes 2 through 5 REGISTER P A R AMETER Drive ID Code as previously defined. Head (side) number. 0 to I for floppy drives 0 to 7 for Winchester drives Track number.

  • Page 154: Function Code 8 — Return Current Drive Parameters

    page 9.11 Disk Drives Function Code 8 — Return Current Drive Parameters When completed, DL contains the number of active Winchester drives, DH contains a number representing maximum usable heads, CH contains a number represent- ing maximum usable cylinders, and CL contains a number representing maximum usable sectors with the two MSBs representing the two MSBs of the maximum...

  • Page 155: Drive Functions

    Page 9.12 Disk Drives Error Status Codes All of the drive function calls will return a status code in register AH upon comple- tion. AH will either contain 0 if the carry flag is not set, or a value representing a specific error if the carry flag is set.
  • Page 156 Page 9.13 Disk Drives Booting an Operating System An operating system may be booted from a specified drive. Register DL should contain the drive number, and if the drive is a Winchester, AL should contain a partition number between 0 and 3 expressed in ASCII (30H to 33H) with 0 representing the default partition.
  • Page 158 Index NOTE: To locate a subject in this manual, first check the Contents for the location of general subjects or illustrations. 8088 microprocessor, 1.2, 3.3 8087 coprocessor, 1.2, 3.3 DIP switch setting, 4.4 80C88 microprocessor, 1.2 Address logic, 6.6 Alphabetic keys, 5.4 Audio speaker, 1.3 Autoboot, 2.2 Floppy disk, 4.6...
  • Page 159 Index 2 Index CPU, 3.3 Card, 2.2, Failure, 2.3 Subsystem, 3.3 System functions, 4.8 Coprocessor, see 8087 coprocessor CRC error, 2.4 Cursor Characteristics, 7.23 Movement, 7.25 CURSOR, 7.18 DIP switches, 2.2, 2.3 Disk-Based Diagnostics, 2.2 Disks, Error messages, 2.4 Formatting, 9.10 Disk drives, 1.3 DIP switch setting, 4.4, 4.5 Error messages, 2.4, 9.12...
  • Page 160 Index 3 Index IBM PC, 6.3, 8.2 Color graphics, 1.2, 2.14 XT, 1.2 Input from port, 2.10 Input/Output, 1.3 Intel, see 8087 coprocessor, 8088 microprocessor Interrupts, 2.7 Invalid address mark detected, 2.4 Invalid/No keyboard code received, 2.4 Keyboard, 1.2, 2.4 Buffer, 5.18 Operation codes, 5.2-5.3 KEYBOARD TEST, 2.
  • Page 161 Index 4 Index Monitors, 1.2 Graphics, 7.9 RGB color, 1.2, 2.5, 7.1 Monochrome composite, 1.2, 7.1 Monochrome display, 7.11 Polarity, 7.6 ROM, 2.2 see ROM, monitor Sync frequency, 4.7 Monitor line length, 4.4, 4.5 Move memory block, 2.11 MS-DOS, 1.3, 2.2, 2.7 Nonalphabetic keys, 5.6 Numeric data coprocessor, see 8087 coprocessor NUM LCK,...
  • Page 162 Index 5 Index Program execution, 2.10 Program interrupt controller, 3.3 Prompt, see ROM monitor prompt Protocol, 8.5 Random Access Memory, see RAM RAM, 2.5, 6.2 Video RAM, 2.2, 2.3, 2.5 Failure, 2.3 Read-Only Memory, see ROM Resolution, 7.11 RGB color monitor, see Monitor ROM, Monitor prompt, 2.7 Checksum failure, 2.3...
  • Page 163 Index 6 Index Video, Card, 1.2, 2.5 Enable bit, 7.19 Mode selection, 2.14 VSYNC, 7.18, 7.24 Winchester drives, 1.3, 9.10, 9.13 Winchester drive controller, 9.2 Configuration, 9.2...

Table of Contents