Memory Subsystem - HP ProLiant DL560 Technology Brief

the processor uses the cache to hold the most recently used information close for faster and more
efficient access.
Typically, there are two levels of cache memory: primary Level 1 (L1) cache and secondary Level 2
(L2) cache. The L1 cache resides within the processor core and holds 8 kilobytes (KB) of recently
accessed data. In addition to this L1 cache, the Intel Xeon processor MP also includes an Execution
Trace Cache that stores up to 12 KB of decoded micro-operations instructions to speed up instruction
throughput and improve response times.
The Intel Xeon processor MP has a 512-KB L2 Advanced Transfer Cache that consists of a
256-bit (32-byte) interface that transfers data on each core clock. This L2 cache stores recently
accessed data that is not being held in the L1 cache. When the processor needs data, it first looks in
the L1 cache. If the information is in the L1 cache (known as a cache hit), the processor uses it without
a performance delay. If the information is not in the L1 cache, the processor next searches the L2
cache.
In the L2 cache, stored data is organized in columns and rows. Each row, or cache line, contains 64
bytes (512 bits) of data. To optimize performance, the OS writes data to or reads data from the L2
cache as a complete 512-KB cache line. The 512-bit cache line size in the Intel Xeon Processor MP is
twice the size of the cache line in the Intel Pentium® III processor. As a result, there is greater chance
of a cache hit for any given memory request.
When a cache hit occurs in the L2 cache, the data is transferred at 2.8 GHz to the processor core
along a 32-byte interface on each core clock cycle. As a result, the 512-KB L2 Advanced Transfer
Cache can deliver a data transfer rate of 89.6 GB/s to the processor so that it can keep executing
instructions instead of sitting idle. This compares to a transfer rate of 16 GB/s for the 1-GHz Intel
Pentium III processor.
To improve performance of enterprise class applications, the Intel Xeon processor MP also includes an
integrated L3 cache available in 2-MB or 1-MB options. Coupled with the 400-MHz system bus, this
L3 cache provides a high bandwidth path to memory. The integrated L3 cache provides a fast path to
large data sets stored in cache on the processor. The result is reduced average memory latency and
increased throughput for large server workloads.
Note:
ProLiant DL560 servers with Intel Xeon processors MP that run at 1.50,
1.90, 2.0, or 2.5 GHz have a 1-MB L3 cache; ProLiant DL560 servers with
Intel Xeon processors MP that run at 2.00 and 2.8 GHz have a 2-MB L3
cache.

Memory subsystem

The hyper-dense ProLiant DL560 server contains six memory sockets. To provide the desired memory
capacity and performance, this server uses 200-MHz Double Data Rate (DDR) Synchronous Dynamic
Random Access Memory (SDRAM); that is, PC2100 Registered SDRAM. DDR SDRAM is a next-
generation SDRAM technology. SDRAM data is transferred on the rising edge of every clock cycle.
However, the memory chip on DDR DIMMs performs transactions on both the rising and falling edges
of the clock cycle, effectively doubling memory bus clock rate yields. With a doubling of the clock
rate yields, the 200-MHz memory bus matches the throughput of the 400-MHz front side bus of the
Intel Xeon Processor MP. The GC-LE chipset provides dual memory channels that provide
3.2 GB/s bandwidth.
The ProLiant DL560 server comes standard with 1024 MB of system memory on most models and is
expandable to 12 GB. Because the ProLiant DL560 features 2-way memory interleaving architecture
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