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For more information, see Chapter 9, "L2 Cache Interface Operation."
1.2.6 System Interface/Bus Interface Unit (BIU)
The address and data buses operate independently; address and data tenures of a memory
access are decoupled to provide a more flexible control of memory traffic. The primary
activity of the system interface is transferring data and instructions between the processor
and system memory. There are two types of memory accesses:
•
Single-beat transfers-These memory accesses allow transfer sizes of 8, 16,24,32,
or 64 bits in one bus clock cycle. Single-beat transactions are caused by uncacheable
read and write operations that access memory directly (that is, when caching is
disabled), cache-inhibited accesses, and stores in write-through mode.
Four-beat burst (32 bytes) data transfers-Burst transactions, which always transfer
an entire cache block (32 bytes), are initiated when an entire cache block is
transferred. Because the first-level caches on the MPC750 are write-back caches,
burst-read memory, burst operations are the most common memory accesses,
followed by burst-write memory operations, and single-beat (noncacheable or write-
through) memory read and write operations.
The MPC750 also supports address-only operations, variants of the burst and single-beat
operations, (for example, atomic memory operations and global memory operations that are
snooped), and address retry activity (for example, when a snooped read access hits a
modified block in the cache). The broadcast of some address-only operations is controlled
through HIDO[ABE]. I/O accesses use the same protocol as memory accesses.
Access to the system interface is granted through an external arbitration mechanism that
allows devices to compete for bus mastership. This arbitration mechanism is flexible,
allowing the MPC750 to be integrated into systems that implement various fairness and bus
parking procedures to avoid arbitration overhead.
Typically, memory accesses are weakly ordered-sequences of operations, including
load/store string and multiple instructions, do not necessarily complete in the order they
begin-maximizing the efficiency of the bus without sacrificing data coherency. The
MPC750 allows read operations to go ahead of store operations (except when a dependency
exists, or in cases where a noncacheable access is performed), and provides support for a
write operation to go ahead of a previously queued read data tenure (for example, letting a
snoop push be enveloped between address and data tenures of a read operation). Because
the MPC750 can dynamically optimize run-time ordering of load/store traffic, overall
performance is improved.
The system interface is specific for each PowerPC microprocessor implementation.
The MPC750 signals are grouped as shown in Figure 1-3. Signals are provided for clocking
and control of the L2 caches, as well as separate L2 address and data buses. Test and control
signals provide diagnostics for selected internal circuits.
Chapter 1. Overview
1-15
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