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10.3.2.3 MPC750 Junction Temperature Determination
While the MPC750's TAU does not implement an analog-to-digital converter to enable the
direct determination of the junction temperature, system software can execute a simple
successive approximation routine to find the junction temperature ..
The TAU configuration used to approximate the junction temperature is the same required
for single-threshold mode, except that the threshold SPR selected has its TIE bit cleared to
o
to disable thermal management interrupt generation. Once the TAU is enabled, the
successive approximation routine loads a threshold value into the active threshold SPR, and
then continuously polls the threshold SPRs TIV bit until it is set to 1, indicating a valid TIN
bit. The successive approximation routine can then evaluate the TIN bit value, and then
increment or decrement the threshold value for another comparison. This process is
continued until the junction temperature is determined.
10.3.2.4 Power Saving Modes and TAU Operation
The static power saving modes provided by the MPC750 (the nap, doze, and sleep modes)
allow the temperature of the processor to be lowered quickly, and can be invoked through
the use of the TAU and associated thermal management interrupt. The TAU remains
operational in the nap and doze modes, and in sleep mode as long as the SYSCLK signal
input remains active. If the SYSCLK signal is made static when sleep mode is invoked, the
TAU is rendered inactive. If the MPC750 is entering sleep mode with SYSCLK disabled,
the TAU should be configured to disable thermal management interrupts to avoid an
unwanted thermal management interrupt when the SYSCLK input signal is restored.
10.4 Instruction Cache Throttling
The MPC750 provides an instruction cache throttling mechanism to effectively reduce the
instruction execution rate without the complexity and overhead of dynamic clock controL
Instruction cache throttling, when used in conjunction with the TAU and the dynamic power
management capability of the MPC750, provides the system designer with a flexible means
of controlling device temperature while allowing the processor to continue operating.
The instruction cache throttling mechanism simply reduces the instruction forwarding rate
from the instruction cache to the instruction dispatcher. Normally, the instruction cache
forwards four instructions to the instruction dispatcher every clock cycle if all the
instructions hit in the cache. For thermal management the MPC750 provides a supervisor-
level instruction cache throttling control (ICTC) SPR. The instruction forwarding rate is
reduced by writing a nonzero value into the ICTC[FI] field, and enabling instruction cache
throttling by setting the ICTC[E] bit to 1. The overall junction temperature reduction results
from dynamic power management reducing the power to the execution units while waiting
for instructions to be forwarded from the instruction cache; thus, instruction cache
throttling does not provide thermal reduction unless HIDO[DPM] is set to 1. Note that
during instruction cache throttling the configuration of the PLL and DLL remain
unchanged.
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MPC750 RISC Microprocessor User's Manual
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