Device Memory Map; Table 1-1 Device Memory Map - Motorola MC9S12DT256 User Manual

MC9S12DT256 Device User Guide — V03.07

1.5 Device Memory Map

Table 1-1 and Figure 1-2 show the device memory map of the MC9S12DT256 after reset. Note that after
reset the bottom 1k of the EEPROM ($0000 - $03FF) are hidden by the register space.
$0000 - $0017
$0018 - $0019
$001A - $001B Device ID register (PARTID)
$001C - $001F CORE (MEMSIZ, IRQ, HPRIO)
$0020 - $0027
$0028 - $002F
$0030 - $0033
$0034 - $003F
$0040 - $007F
$0080 - $009F
$00A0 - $00C7 Pulse Width Modulator 8-bit 8 channels (PWM)
$00C8 - $00CF Serial Communications Interface (SCI0)
$00D0 - $00D7 Serial Communications Interface (SCI1)
$00D8 - $00DF Serial Peripheral Interface (SPI0)
$00E0 - $00E7 Inter IC Bus
$00E8 - $00EF Byte Data Link Controller (BDLC)
$00F0 - $00F7
$00F8 - $00FF Serial Peripheral Interface (SPI2)
$0100- $010F
$0110 - $011B
$011C - $011F Reserved
$0120 - $013F
$0140 - $017F
$0180 - $01BF Motorola Scalable Can (CAN1)
$01C0 - $01FF Reserved
$0200 - $023F
$0240 - $027F
$0280 - $02BF Motorola Scalable Can (CAN4)
$02C0 - $03FF Reserved
$0000 - $0FFF EEPROM array
24

Table 1-1 Device Memory Map

Address
CORE (Ports A, B, E, Modes, Inits, Test)
Reserved
Reserved
CORE (Background Debug Mode)
CORE (PPAGE, Port K)
Clock and Reset Generator (PLL, RTI, COP)
Enhanced Capture Timer 16-bit 8 channels
Analog to Digital Converter 10-bit 8 channels (ATD0)
Serial Peripheral Interface (SPI1)
Flash Control Register
EEPROM Control Register
Analog to Digital Converter 10-bit 8 channels (ATD1)
Motorola Scalable Can (CAN0)
Reserved
Port Integration Module (PIM)
Module
Size
(Bytes)
24
2
2
4
8
8
4
12
64
32
40
8
8
8
8
8
8
8
16
12
4
32
64
64
64
64
64
64
320
4096