Powerpc Registersñuser Registers; Powerpc User-Level Register Bit Assignments; Condition Register (Cr) - Motorola MPC860 PowerQUICC User Manual

Part II. PowerPC Microprocessor Module
5.1.1 PowerPC RegistersÑUser Registers
The MPC860 implements the user-level registers defined by the PowerPC architecture
except those required for supporting ßoating-point operations (the ßoating-point register
Þle (FPRs) and the ßoating-point status and control register (FPSCR)). User-level,
PowerPC registers are listed in Table 5-1 and Table 5-2. Table 5-2 lists user-level
special-purpose registers (SPRs).
Description Name
General-purpose GPRs The thirty-two 32-bit (GPRs) are used for source
registers
Condition register CR
Table 5-2 lists SPRs deÞned by the PowerPC architecture implemented on the MPC860.
SPR Number
Decimal SPR [5Ð9] SPR [0Ð4]
1 00000 00001
8 00000 01000
9 00000 01001
268 01000 01100
269 01000 01101
1
Extended opcode for mftb, 371 rather than 339.
2
Any write (mtspr) to this address causes an implementation-dependent software emulation exception.

5.1.1.1 PowerPC User-Level Register Bit Assignments

This section describes bit assignments of PowerPC registers implemented by the MPC860.
For more details, see the Programming Environments Manual for 32-Bit Processors.
5.1.1.1.1 Condition Register (
The condition register (CR) is a 32-bit register that reßects the result of certain operations
and provides a mechanism for testing and branching. The bits in the CR are grouped into
eight 4-bit Þelds, CR0ÐCR7, as shown in Figure 5-1.
CR0 CR1
0 3 4
5-2
Table 5-1. User-Level PowerPC Registers
Comments
and destination operands.
See Section 5.1.1.1.1, ÒCondition Register
(CR).Ó
Table 5-2. User-Level PowerPC SPRs
Name Comments
XER See Section 5.1.1.1.3,
ÒXER.Ó
LR See the Programming
Environments Manual
CTR See the Programming
Environments Manual
1
TBL read Section 11.9, ÒThe
PowerPC Timebase.Ó
2
TBU read
CR)
CR2 CR3
7 8 11 12 15
Figure 5-1. Condition Register (CR)
MPC860 PowerQUICC UserÕs Manual
Access Level Serialize Access
Serialize Access
Write: Full sync
Read: Sync relative to load/store operations
No
No
Write (as a store)
CR4 CR5
16 19 20 23
User Ñ
User Only mtcrf
CR6 CR7
24 27 28 31
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