Processor Type Identification; Processor Pll Configuration; L1, L2, L3 Cache; Table 2-9. Processor L3Cr Register Assignments - Motorola MVME5500 Programmer's Reference Manual

Programming Details
2

Processor Type Identification

Processor PLL Configuration

L1, L2, L3 Cache

2-16
Microprocessor User's Manual, listed in
Documentation, for details.
Software can determine the processor version through the version register.
The most significant 16 bits (0:15) of the MPC7455 processor version
register reads as 0x8001.
The processor internal clock frequency (core frequency) is a multiple of
the system bus frequency. The processor has five configuration pins,
PLL_EXT and PLL_CFG[0:3], for hardware strapping of the processor
core frequency (between 2x and 16x of the system bus frequency).
The processors support on-chip L1 and L2 caches and external L3 cache.
L3 cache supports 1 or 2MB in a variety of SRAM device types. Each
processor L3 interface on the MVME5500 consists of two 8Mb devices
(K7D803671B-HC30) providing a total of 2MB of L3 cache. Data parity
checking should be enabled. The following processor L3CR register
settings assume a processor speed of 933 MHz and L3 clock speed of
233 MHz.

Table 2-9. Processor L3CR Register Assignments

Apollo L3CR
Register Description
L3SIZ L3 Size, 2 MB
L3RT L3 SRAM Type, DDR SRAM
Appendix B, Related
Computer Group Literature Center Web Site
Value
1
00