Chapter 4. Lcd Unit - Sharp PC-4741 Service Manual

CHAPTER 4. LCD UNIT
-
P C-4741
For the scan start signal S has been transferred at the first line to
display the data by the combination of the LCD scan electrode and
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While the first line data are being displayed, the second line display
4-1. Structure
A 640
x
400 full dot graphics display unit is employed for the LCD unit
which consists of a printed circuit board that contains the LCD panel
and its electronic cirCUits, an electrically connected film carrier LSI
chip, and a mechanically held plastic chassis, and a bezel.
4-2. Operational theory
Circuit block diagram and interface signals are shown in the figure
next.
LC
"
DLO' 1
~
LeDUO-LeCU3
DUO-3
g~~
CPI
S
Is
II
B-
M
1
I
SEG drivers (Upper)
I
L.,
j
40 X 400 LCD
p a n a l -
,
signal generation d.cult
;=
0
0
'M
-
I
SEG drivers (Lower)
vee
eND
VLCD
3r
iaS
voltsgaI
generation
circuli I
LCDLO-LCOL3
YI
I CirCUIt bock diagram
Interface signals
Pin
NO.
Symbol Description
1 S
Scan start signal
2 CP1 Input data latch signal
3
CP2 Data input clock signal
4 PVBKL Back light power control signal
5 GND Ground
6
VLCD
liqUid crystal drive power (-)
7 LCDUO Display data signal (upper halD
8 LCDU1 "
9 LCDU2 "
10 LCDU3 "
11 LCDLO Display data signal (lower halD
12 LCDL1
"
13 LCDL2
"
14 LCDL3
"
I
Active signal level
nH"
H .... L
H .... L
H (ON), L (OFF)
-
-
H(ON), L(OFF)
"
"
"
H(ON), L(OFF)
"
"
"
The display screen of this unit is configured of 640 x 400 dots two
screens, each screen driven with 1/200 duty.
An BO-pin LSI is used for the LCD driver that consists of a shift
register, latch, and LCD drive circuit.
Data are inputted for each line (640 dots) of the screen. From the left
side of the screen, 4-bit parallel data are sent one at a time via the
shift register with the clock pulse CP2. When the 640 dots data have
been received for one display line, the data are latched as a parallel
data with respect to the 640 signal electrodes at a high to low transi-
tion of the latch signal CP1 to send the drive signal by the drive circuit
to the corresponding electrodes.
-23-
data are received. Upon completing transfer of 640 data, it will then
be latch at a high to low transition of CP1 to change it to display the
second line.
In this way, data input are repeated to the 200th line from top to
bottom using the multiplexed method. After completion of one screen
(one frame), data are then received from the first line again. The scan
start signal S is the scan signal to drive horizontal electrode.
For it causes the liquid crystal elements to deteriorate because of
chemical reaction if DC voltage is added to the LCD panel, the drive
signal waveform must be inverted at every screen in order to avoid
generation of DC voltage. The circuit employed to do this is the async
M signal circuit from which generated the drive waveform AC signal
M.
Because of the characteristics of the CMOS driver LSI, power con-
sumption increases as CP2 clock frequency increases. Therefore, it
incorporates four
sh~ft
registers to transfer the 4-bit parallel data via
these shift registers to decrease the CP2 clock data transfer speed. In
this circuit, a 4-bit display data (LCDUO - 3 for upper half screen and
LCDLO -
3 for
lower half screen) are supplied through the data input
lines.
To further abate the power consumption, it also has a data input bus
line system which comes operating only when appropriate data are
received.
The following shows the screens signal electrode data inputs vs.
driver LSI chip select signal.
The driver LSI of the left end screen is first elected. When the SO-dot
data (20CP2) has been supplied, the driver LSI adjacent to right is
then selected. This continues until the data are sent to the driver LSI
at the screen right.
This process occurs Simultaneously for signal electrode signal LSls of
both screens. In this manner, data of both screens are supplied via
4-bit bus line starting from the left end of the screen.
For the graphics display unit does not contain the refresh RAM, it
becomes necessary to input the data and timing pulse when the
screen is still.
The following shows the dot table of the display, data input timing
chart, and input signal timing.
ldot
2dol
3dot
20Odot
201dot
40Odol
ldol
,,' "
3dot 64Qdot
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t . ,
-----
........
--
..
----
....
---
...
---
..
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,
,
."
.~
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S
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• • • • • • • • • u • • • • • • • u u u u u u u • • • • • • • • • • • • • • • • • • • • •
i400.640j
NOTE: 1 aoo21ndicale li'Sl horizontal dol and sec:OnddoL
Olsplil)' dOlchart.