Page 1 Freescale Semiconductor, Inc. MOTOROLA Metrowerks SW/HW Dept MSC8101 ADS User’s Manual Revision B (Revision Release 1.2) Dragilev Lev SW/HW Dept Motorola Semiconductor Israel 1 Shenkar Street, Herzlia 46120, Israel 972-9-522-579 email: Lev.Dragilev@motorola.com FAX: 972-9-9562990 25/1/2004 For More Information On This Product,...
Page 2 Freescale Semiconductor, Inc. MSC8101ADS RevB User’s Manual For More Information On This Product, Go to: www.freescale.com...
Page 3: Table Of Contents
Freescale Semiconductor, Inc. 1•1 Introduction 1•2 Abbreviations’ List 1•3 Related Documentation 1•4 Specification 1•5 ADS Features 2•1 INTRODUCTION 2•2 UNPACKING INSTRUCTIONS 2•3 HARDWARE PREPARATION 2•3•1 Setting The Core Supply Voltage Level 2•3•2 Setting MODCK(1:3) For Initial PLLs’ Multiplication Factor - SW9 2•3•3 Setting HReset Configuration Source 3•1...
Page 4 Freescale Semiconductor, Inc. 4•4•4 Ethernet LINK Indicator - LD4 4•4•5 Fast Ethernet CLSN Indicator - LD5 4•4•6 ATM RX Indicator - LD6 4•4•7 ATM TX Indicator - LD7 4•4•8 TEXP Indicator - LD8 4•4•9 Signaling Indicator 1 - LD9 4•4•10 Signaling Indicator 0 - LD10 4•4•11 RS232 Port 2 ON - LD11...
Page 5 Freescale Semiconductor, Inc. 5•11•1 BCSR0 - Board Control / Status Register 0 5•11•2 BCSR1 - Board Control / Status Register 1 5•11•3 BCSR2 - Board Control / Status Register 2 5•11•4 BCSR3 - Board Status Register 3 7•1 Power rails. 7•1•1 5V Bus 7•1•2...
Page 6 Freescale Semiconductor, Inc. MSC8101ADS RevB User’s Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 7 Freescale Semiconductor, Inc. FIGURE 1-1 MSC8101ADS Block Diagram FIGURE 2-1 MSC8101ADS Top Side Part Location diagram FIGURE 3-1 Host System Debug Scheme A FIGURE 3-2 Host System Debug Scheme B FIGURE 3-3 Stand Alone Configuration FIGURE 3-4 P26: +5V Power Connector FIGURE 3-5 P6 - JTAG/OnCE Port Connector FIGURE 3-6...
Page 8 Freescale Semiconductor, Inc. MSC8101ADS RevB User’s Manual MOTOROLA VIII For More Information On This Product, Go to: www.freescale.com...
Page 9: List Of Tables
Freescale Semiconductor, Inc. LIST OF TABLES TABLE 1-1. MSC8101ADS Specifications TABLE 4-1. Available Clock Mode Setting TABLE 4-2. JP1/JP2 Settings TABLE 4-3. SIU Registers’ Programming TABLE 4-4. Memory Controller Initialization for 100(50) MHz TABLE 5-1 Summary Reset Configuration Schemes. TABLE 5-2. Hard Reset Configuration Word TABLE 5-3.
Page 10 Freescale Semiconductor, Inc. MSC8101ADS RevB User’s Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 11: Introduction
Freescale Semiconductor, Inc. 1 - General Information 1•1 Introduction This document describes the engineering specifications of the MSC8101ADS board based on the MSC8101- first member of the family of programmable DSP based around the SC100 DSP cores. It integrates a high-performance Star*Core SC140 DSP is four ALU DSP Core, large on-chip memory (1/2 MByte), Communication Processor Module compatible with PowerQUICCII (MPC8260) CPM, a very flexible system integration unit (SIU) and a 16-channel DMA engine.
Page 12: Specification
Freescale Semiconductor, Inc. PMC-SIERRA 5350 Long Form Data Sheet PMC-SIERRA 5350 Errata Notice PMC-SIERA 5350 Reference Design LXT970A (by Level One) Data Sheet LXT970 Demo Board User’s Guide 1•4 Specification The MSC8101ADS specifications are given in TABLE 1-1. MSC8101ADS Specifications CHARACTERISTICS Power requirements (no other boards attached) MSC8101...
Page 13: Ads Features
Freescale Semiconductor, Inc. 1•5 ADS Features 64-bit MSC8101, running up to @ 100MHz external bus frequency. 8 MByte, 80 pin Flash SIMM reside after buffer. Support for up to 32 MByte, con- trolled by GPCM, 5V Programmable, with Automatic Flash SIMM identification, via BCSR.
Page 14 Freescale Semiconductor, Inc. On-board 1.2V - 2.2V adjustable for MSC8101 Internal Logic Operation and 3.3V±10% fixed Voltage Regulators for other circuits. May be bypassed in case of external power supplying. Software Option Switch provides 8 S/W options via BCSR. LED’s for power supply, module enables, timer expired and SW indications. MSC8101ADS RevB User’s Manual For More Information On This Product, General Information...
Page 15: Figure 1-1 Msc8101Ads Block Diagram
Freescale Semiconductor, Inc. FIGURE 1-1 MSC8101ADS Block Diagram Clock D[32:59] 16.4/25MHz Ext CLK Reset,Config Interrupts DATA Transceivers & Address Buffers D[0:31] MSC8101 332 pin 0.8mm 19x19 matrix (3M Socket) Clock Buffer ClkOut 14pin JTAG/OnCE DLLIN SCC1,SMC1 Command Converter FCC2 MIIctrl. FCC1 3.3V QFALC...
Page 16: Introduction
Freescale Semiconductor, Inc. 2 - Hardware Preparation 2•1 INTRODUCTION This chapter provides unpacking instructions, hardware preparation, and installation instructions for the MSC8101ADS 2•2 UNPACKING INSTRUCTIONS If the shipping carton is damaged upon receipt, request carrier’s agent to be present during unpacking and inspection of equipment.
Page 17: Figure 2-1 Msc8101Ads Top Side Part Location Diagram
Freescale Semiconductor, Inc. Hardware Preparation FIGURE 2-1 MSC8101ADS Top Side Part Location diagram Boot Mode SW S/W Opt EE SW 64/32 Select Host SW Config SW MSC8101ADS RevB User’s Manual MOTOROLA For More Information On This Product, Go to: www.freescale.com...
Page 18: Setting The Core Supply Voltage Level
Freescale Semiconductor, Inc. 2•3•1 Setting The Core Supply Voltage Level The internal Logic & PLL’s of the MSC8101 is powered separately through a supply bus named 1V5. The voltage level over this power bus may vary between 0.9V - 2.1V. In the lower voltage level, the Processor will operate at lower frequency range, consuming a smaller amount of power and vice-versa for the higher voltage level.
Page 19: Once Connection Scheme
Freescale Semiconductor, Inc. 3 - Installation Instructions The MSC8101ADS may be configured according to the required working environment as follows: • Host Controlled Operation through OnCE Port • Host Interface Operation through HDI16 Port • Stand-Alone Mode 3•1 OnCE Connection Scheme In this configuration the MSC8101ADS is controlled by a host computer via the OnCE Port, which is a subset of the JTAG port.
Page 20: Stand Alone Operation
Freescale Semiconductor, Inc. FIGURE 3-2 Host System Debug Scheme B Host Computer Command Media I/F Converter 3•3 Stand Alone Operation In this mode, the ADS is not controlled by the host via the OnCE port. It may connect to host via one of its other ports, e.g., RS232 port, Fast Ethernet port, ATM155 port etc.
Page 21: +5V Power Supply Connection
Freescale Semiconductor, Inc. FIGURE 3-3 Stand Alone Configuration 5V Power Supply 3•4 +5V Power Supply Connection The MSC8101 requires +5V DC @ 4A max, power supply for operation. Connect the +5V power supply to connector P26 as shown below: FIGURE 3-4 P26: +5V Power Connector P26 is a 3 terminal block power connector with power plug.
Page 22: Host I/F Connector - P4
Freescale Semiconductor, Inc. supplied with the Command Converter obtained from Macraigor Systems. JTAG/OnCE Port Connector" below FIGURE 3-5 P6 - JTAG/OnCE Port Connector 3•6 HOST I/F Connector - P4 The MSC8101ADS HOST I/F connector, P4, is a 36 pin, two rows, header connector. The connection between the MSC8101-ADS and the Host Board is by a 36 line flat cable, not shipped with the ADS.
Page 23: Terminal To Msc8101Ads Rs-232 Connection
Freescale Semiconductor, Inc. FIGURE 3-6 P4 - Host I/F Connector HRRQACK 3•7 Terminal to MSC8101ADS RS-232 Connection A serial (RS232) terminal or any other RS232 equipment, may be connected to both connectors P27/A-B (Upper and Lower). This connectors are a 9 pin, female, D-type connectors, arranged in a stacked configuration.
Page 24: 10/100-Base-T Ethernet Port Connection
Freescale Semiconductor, Inc. FIGURE 3-7 P27A - Upper RS-232 Serial Port Connector FIGURE 3-8 P27B - Lower RS-232 Serial Port Connector 3•8 10/100-Base-T Ethernet Port Connection The 10/100-Base-T port connector - P12, is an 8-pin, 90 nection between the 10/100-Base-T port to the network is done by a standard cable, having two RJ45/8 jacks on its ends.
Page 25: Figure 3-9 Flash Memory Simm Insertion
Freescale Semiconductor, Inc. The memory SIMMs have alignment nibble near their # 1 pin. It is important to align the memory correctly before it is twisted, other- wise damage might be inflicted to both the memory SIMM and its socket. FIGURE 3-9 Flash Memory SIMM Insertion Metal Lock Clip SIMM...
Page 26: Introduction
Freescale Semiconductor, Inc. 4 - Operating Instructions 4•1 INTRODUCTION This chapter provides necessary information to use the MSC8101-ADS in host-controlled and stand-alone configurations. This includes controls and indicators, memory map details, and software initialization of the board. 4•2 SWITCHES The MSC8101ADS has the following switches: 4•2•1 Host I/F Setting - SW1 This switch is using for manually set a Host Bus parameters.
Page 27: Abort Switch - Sw3
Freescale Semiconductor, Inc. FIGURE 4-2 Switch SW2 - Description RESERVED Set to ‘0’ <= 4•2•3 ABORT Switch - SW3 The ABORT switch is normally used to abort program execution, this by issuing a level 0 non- maskable interrupt to the Processor. If the ADS is in stand alone mode, it is the responsibility of the user to provide means of handling the interrupt, since there is no resident debugger with the MSC8101-ADS.
Page 28: Hard Reset (Hreset) - Switch - Sw7
Freescale Semiconductor, Inc. FIGURE 4-3 DIP-Switch 64/32 Bit Setting 4•2•6 HARD RESET (HRESET) - Switch - SW7 HARD reset is generated when switch SW7 is pressed. When the Processor executes HARD reset sequence, all its configuration is lost, including data stored in the SDRAMs and the Processor has to be re-initialized.
Page 29: Boot Mode Select - Sw10
Freescale Semiconductor, Inc. FIGURE 4-4 Switch SW9 MODCK - Description HOST FCFG MODCK6 MODCK5 MODCK4 MODCK3 MODCK2 MODCK1 Set to ‘0’ <= TABLE 4-1. Available Clock Mode Setting MODCK- a. Factory setting. b. Alternative clock mode for 100MHz bus frequency requires clock oscillator 20MHz 4•2•9 Boot Mode Select - SW10 SW10 is a 4-switch Dip-Switch with three poles in use.
Page 30: Software Options Switch - Sw11
Freescale Semiconductor, Inc. FIGURE 4-5 Switch SW10 BOOT MODE - Description RESERVED BTM1 BTM0 Set to ‘0’ <= 4•2•10 Software Options Switch - SW11 SW11 is a 4-switch Dip-Switch with three poles in use. This switch is connected over SWOPT(0:2) lines which are available at BCSR2 via bus driver U16, S/W options may be manually selected, according to SW11 state.
Page 31: Jp3 - 50 Ohm Enable
Freescale Semiconductor, Inc. DLL. See TABLE 4-2. summarized available modes. . Default set is JP3-OPEN (DLL disable). TABLE 4-2. JP1/JP2 Settings OPEN CLOSE 4•3•3 JP3 - 50 Ohm Enable. JP3 provides 50 Ohm resistance termination in case when using an external clock source via coaxial cable connected to the SMB CLOCKIN.
Page 32: Js1-5 - Current Consumption Measurement
Freescale Semiconductor, Inc. FIGURE 4-8 JP9 - 5V CODEC Source Selection 5V Internal Factory Set 4•3•8 JS1-5 - Current Consumption Measurement JS1-5 reside on I/O-pins, core & PLL main flow. To measure current consumption, the correspond- ing JS should be removed using a solder tool and a current meter (shunt) should be connected instead, with as shorted and thicker wires as possible.
Page 33: Ethernet Link Indicator - Ld4
Freescale Semiconductor, Inc. The green Ethernet Receive LED indicator blinks whenever the LXT970 is transmitting data via the 10/100-Base-T port. 4•4•4 Ethernet LINK Indicator - LD4 The yellow Ethernet Twisted Pair Link Integrity LED indicator - LINK, lights to indicate good link integrity on the 10/100-Base-T port.
Page 34: Atm On - Ld14
Freescale Semiconductor, Inc. Application S/W should always seek to match the state of LD13 to the status of the LXT970, so that, this indication is made reliable as to the correct status of the LXT970. 4•4•14 ATM ON - LD14 When the yellow ATM ON LED is lit, it indicates that the ATM-UNI transceiver - the PM5350, is active and enables communication via that medium.
Page 35: System Initialization
Freescale Semiconductor, Inc. • PPC Bus SDRAM Controller • GPCM (Flash, BCSR, ATM, Ext. Tools) • UPM (QFALC, Ext. Tools) Communication functions which include: • ATM SAR • Fast Ethernet controller. • TDMs for T1/E1 and CODEC support • UART for terminal or host computer connection. The internal registers of the MPC must be programmed after Hard reset as described in the following paragraphs.
Page 36: Table 4-4. Memory Controller Initialization For 100(50) Mhz
Freescale Semiconductor, Inc. The initialization in ler Initialization for 100(50) MHz" below on design and are not verified yet, due to silicon availability problems. TABLE 4-4. Memory Controller Initialization for 100(50) Reg. Device Type SM73228XG1JHBG0 by Smart Modular Tech. SM73248XG2JHBG0 by Smart Modular Tech.
Page 37 Freescale Semiconductor, Inc. TABLE 4-4. Memory Controller Initialization for 100(50) Reg. Device Type PM5350 - ATM UNI User’s peripheral User’s peripheral BR10 DSPRAM OR10 BR11 DSP Peripherals OR11 PSDMR SDRAM 64bit SDRAM 32bit PSRT SDRAM Supported MPTPR SDRAM Supported MSC8101ADS RevB User’s Manual MOTOROLA For More Information On This Product, Operating Instructions...
Page 38 Freescale Semiconductor, Inc. TABLE 4-4. Memory Controller Initialization for 100(50) Reg. Device Type MBMR QFALC - 4ch. T1/E1 Read Access Write Access Exception Access Normal Operation a. Table values in parentheses reflect the lower frequency bus. b. With Host Enable. c.
Page 39: Reset & Reset - Configuration
Freescale Semiconductor, Inc. 5 - Functional Description In this chapter the ADS block diagram is described in detail. 5•1 Reset & Reset - Configuration There are available reset sources on the MSC8101ADS: Power-On-Reset and manual Manual Hard-Reset Manual Soft-Reset JTAG/ONCE - Reset MSC8101 internal Resets.
Page 40: Table 5-1 Summary Reset Configuration Schemes
Freescale Semiconductor, Inc. Hard-Reset configuration word. This configuration may be taken from an internal default, in case RSTCONF is negated during HRESET asserted or taken from the Flash memory (MS 8 bits of the data bus) or Altera device in case RSTCONF signal is asserted along with HRESET. Its meant Hardware Reset Configuration in different of Host Reset Configuration that available while HPE- Host Port Enable input of the MSC8101 is sampled high at the rising edge of PORESET the Host Port is enabled and a Configuration Word is got from Host I/F.
Page 41: Manual Soft Reset
Freescale Semiconductor, Inc. TABLE 5-2. Hard Reset Configuration Word Data Prog Field Value Bits [Bin] IRPC ’00’ DPPC 10:11 ‘00’ NMIOUT ’0’ 13:15 ’000’ ’0’ ’0’ Reserved 18:21 ‘0000’ TCPC 22:23 ’10’ BC1PC 24:25 ’00’ Reserved ’0’ DLLDIS ’1’ MODCK_HI 28:30 ‘111’...
Page 42: Msc8101 Internal Hard Reset Sources
Freescale Semiconductor, Inc. 5•1•5 MSC8101 Internal Hard Reset Sources The MSC8101 has internal sources which generate Hard / Soft Resets. Among these sources are: Loss of Lock Reset (Hard) S/W Watch Dog Reset (Hard) Bus Monitor (Hard) JTAG/ONCE Reset (Hard) In general, the MSC8101 asserts a reset line HARD or SOFT for a period 512 clock cycles after the reset source has been identified.
Page 43: Bus Buffering
Freescale Semiconductor, Inc. FIGURE 5-1 Clock Distribution Scheme MSC8101 CLOCK OSC 55MHz/ CLKIN CLKOUT 20MHz DLL_IN The Zero Delay Buffer CY2309 distributes high speed clock with skew less 250ps when internal PLL is ON. Select inputs S1,S2 allow to the input clock be directly applied to the output with pro- pogation delay of regular clock buffer about 5ns.
Page 44: Synchronous Dram Bank
Freescale Semiconductor, Inc. ceivers are disabled during access to that region, avoiding possible The MSC8101 chip-selects assignment to the various memories / registers on the MSC8101ADS are shown in TABLE 5-3. TABLE 5-3. MSC8101ADS Chip Select Assignments Chip Assignment Select Flash SIMM /BCSR Config Word BCSR SDRAM(soldered on the board)
Page 45: Sdram Programming
Freescale Semiconductor, Inc. assigned to a CS line according to FIGURE 5-2 SDRAM Connection Scheme Address MUX BNK1 BNK0 A(29:19) A(0:9) PSDA10 SYSCLK1 DQM(0:3) D(0:31) SDRAMEN64/32 DQM(4:7) D(32:63) 5•6•1 SDRAM Programming After power-up, SDRAM needs to be initialized by means of programming, to establish its mode of operation.
Page 46: Sdram Refresh
Freescale Semiconductor, Inc. b. Two clocks latency setting is programmed for 50MHz Bus Clock c. 8 beat burst is programmed for 32bit Data Bus width (Host Interface is active) 5•6•2 SDRAM Refresh The SDRAM is refreshed using its auto-refresh mode. I.e., using SDRAM machine 1’s periodic timer, an auto-refresh command is issued to the SDRAM every 14 µsec, so that all 4096 rows are refreshed within spec’d 57.3...
Page 47: Flash Programming Voltage
Freescale Semiconductor, Inc. FIGURE 5-3 FLASH SIMM Connection Scheme BCSR FCSb As can be seen in FIGURE 5-3, the FLASH CS is distributed to four CS signals. The distribution depends on the size of the FLASH module installed - it is read by the BCSR using the PD(1-7) pins. 5•7•1 Flash Programming Voltage Support is given to modules that require 5V for programming.
Page 48: Communication Ports
Freescale Semiconductor, Inc. 5•8 Communication Ports The MSC8101ADS is include several communication ports, to allow convenient evaluation of CPM "Highlights". Obviously, it is not possible to provide all types of communication interfaces support- ed by the CPM, but it is made convenient to connect communication interface devices to the MSC8101 via the CPM Expansion connectors, residing on the edge of the board.
Page 49: Table 5-6. Ports Function Enable
Freescale Semiconductor, Inc. TABLE 5-6. Ports Function Enable MSC8101 I/O Ports/Name PA6/TDMA1-L1RSYNC PA7/TDMA1-L1TSYNC PA8/TDMA1-L1RXD0 PA9/TDMA1-L1TXD0 PA14/MIIRXD3/ATM8-RXD4 PA15//MIIRXD2/ATM8-RXD5 PA16/MIIRXD1/ATM8-RXD6 PA17/MIIRXD0/ATM8-RXD7 PA18/MIITXD0/ATM8-TXD7 PA19/MIITXD1/ATM8-TXD6 PA20/MIITXD2/ATM8-TXD5 PA21/MIITXD3/ATM8--TXD4 PA26/MIIRXER/ATM8-RxClav PA27/MIIRXDV/ATM8-RxSOC PA28/MIITXEN/ATM8-RxEnb PA29/MIITXER/ATM8-TxSOC PA30/MIICRS/ATM8-TxClav PA31/MIICOL/ATM8-TxEnb PB18/MIIRXD3 PB19/MIIRXD2 PB20/TDMD2-L1RSYNC/MIIRXD1 PB21/TDMD2-L1TSYNC/MIIRXD0 PB22//TDMD2-L1RXD/MIITXD0 PB23//TDMD2-L1TXD/MIITXD1 PB24/TDMC2-L1RSYNC/MIITXD2 PB25/TDMC2-L1TSYNC/MIITXD3 PB26/TDMC2-L1RXD/MIICRS PB27/TDMC2-L1TXD/MIICOL PB28/TDMB2-L1TSYNC/MIIRXER PB29/TDMB2-L1RSYNC/MIITXEN PB30/TDMB2-L1RXD/ATM8-MIIRXDV PB31/TDMB2-L1TXD/MIITXER...
Page 50: Atm Port
Freescale Semiconductor, Inc. TABLE 5-6. Ports Function Enable MSC8101 I/O Ports/Name PC30/TDMA1-TXCLK(CLK2) PC31/TDMA1-RXCLK(CLK1) PD30/IDMA2-DRACK/IDMA2-DONE PD31/IDMA1-DRACK/IDMA1-DONE 5•8•1 ATM Port To support the MSC8101 ATM controller, a 155.52Mbps User Network Interface (UNI) is provided on board, connected to FCC1 of the MSC8101 via UTOPIA I/F.Use is done with PM5350 S/UNI- 155-ULTRA by PMC-SIERA.
Page 51: Audio Codec
Freescale Semiconductor, Inc. ethernet transceiver may be Disabled / Enabled at any time via the MII’s MDIO port. The LXT970 is able to interrupt the MSC8101, this via IRQ7~ line. This line is shared also with the CPM expansion connectors. Therefore, any tool that is connect to IRQ7 or IRQ6~ for that matter, should drive these lines only with an Open Drain buffer.
Page 52: T1/E1 Ports
Freescale Semiconductor, Inc. TABLE 5-7. CS4221 Programming Byte Function Num. Converter Status Master Clock 5•8•4 T1/E1 Ports The QFALC framer supports four T1/E1 and contains analog and digital function blocks, which are configured and controlled by MSC8101. Due to its multitude of implemented functions, it fits to a wide range of networking applications and fulfills the according international standards External clock oscillator is mounted on the DIP socket to provide easy changing for both T1 and E1.
Page 53: Host I/F
Freescale Semiconductor, Inc. to detect if a terminal is connected to the MSC8101ADS board. • ( O ) - Data Set Ready. This line is always asserted by the MSC8101ADS. • RTS ( I ) - Request To Send. This line is not connected in the MSC8101ADS. •...
Page 54: Dma Off-Board Tool
Freescale Semiconductor, Inc. pansion Connector is using for off-board tools (ECOM,DMA e.g.) it’s necessary to avoid signal col- lisions. For this purpose Host I/F buffers should be disabled for external non-dedicated tools. The placement Host I/F signals is shown in the following table. TABLE 5-8.
Page 55: Bcsr0 - Board Control / Status Register 0
Freescale Semiconductor, Inc. • Buffers Enable/Disable. • Device Reset. Host Interface which includes: • Buffers Enable/Disable • Host Acknowledge Enable ATM Port Control which includes: • Transceiver Enable / Disable • Device Reset. Fast Ethernet Port Control which includes: • Transceiver Initial Enable •...
Page 56: Bcsr1 - Board Control / Status Register 1
Freescale Semiconductor, Inc. TABLE 5-9. BCSR0 Description MNEMONIC HOSTTRI Host Request or Acknowledge Enable. When high host request/ acknowledge I/O obtains high impedance and external buffer is HI-Z if low this signal is enable via external buffer. T1_1EN T1/E1 channel 1 Enable. When asserted (low) T1/E1 QFALC framer channel 1 lines are connected to the CPM TDMA1 ports.
Page 57 Freescale Semiconductor, Inc. TABLE 5-10. BCSR1 Description MNEMONIC ATM_RST ATM Port Reset. When asserted (low), the ATM port transceiver is in reset state. This line is driven also by HRESET~ signal of the MSC8101. FETHIEN Fast Ethernet Port Initial Enable. When asserted (low) the LXT970’s MII port, residing on FCC2, is enabled after Power-Up or after FETH_RST is negated.
Page 58: Bcsr2 - Board Control / Status Register 2
Freescale Semiconductor, Inc. TABLE 5-11. Peripheral’s Availability Decoding. Enable to: CODEC T1/E1 channels FETH T1/E1 channel a. Power-on default mode is enable for CODEC and disable for the rest peripherals. 5•11•3 BCSR2 - Board Control / Status Register 2 BCSR2 is a status register which is accessed as word at offset 8 from the BCSR base address. Its a Read-Only register which may be read at any time.
Page 59: Bcsr3 - Board Status Register 3
Freescale Semiconductor, Inc. TABLE 5-12. BCSR2 Description MNEMONIC 20 - 23 BREVN(0:3) Board Revision Number (0:3). This field represents the revision code, hard-assigned to the ADS. See on page 61 SWOPT2 Software Option 2. This is the LSB of the field. Shows the state of a dedicated dip-switch providing an option to manually change a program flow.
Page 60: Table 5-15. Bcsr3 Description
Freescale Semiconductor, Inc. tion" on page TABLE 5-15. BCSR3 Description MNEMONIC Emulation Enable 0. Shows the apropriate bit state of the emulation dip- switch providing an option to manually program debugging. Emulation Enable 1. Same as EE0. Emulation Enable 2 Emulation Enable 3.
Page 61: Table 5-16. Extooli(0:3) Assignment
Freescale Semiconductor, Inc. TABLE 5-16. EXTOOLI(0:3) Assignment EXTTOOLI(0:3) [hex] 1 - C TABLE 5-17. External Tool Revision Encoding TOOLREV(0:3) [hex] TABLE 5-18. ADS Revision Encoding Revision Number (0:3) MSC8101ADS RevB User’s Manual MOTOROLA For More Information On This Product, Functional Description External Tool T/ECOM - Communication tool Reserved...
Page 62 Freescale Semiconductor, Inc. 6 - PPC Bus Memory Map All accesses to MSC8101 memory slaves is controlled by the its memory controller. Therefore, the memory map is reprogrammable to the desire of the user. After Hard Reset is performed by the debug station, the debugger checks for existance, size, delay and type of the FLASH memory SIMM mounted on board and initializes the memory controller accordingly.
Page 63: Table 6-1. Msc8101Ads Memory Map
Freescale Semiconductor, Inc. and DMA. This memory map is a recommended memory map and since it is a "soft" map devices’ TABLE 6-1. MSC8101ADS Memory Map ADDESS RANGE Memory Type 00000000 - 0007FFFF Internal SRAM 00080000 - 00EFFDFF Empty Space 00EFFE00 - 00EFFEFF EOnCE Registers 00EFFF00 - 00EFFFFF...
Page 64 Freescale Semiconductor, Inc. TABLE 6-1. MSC8101ADS Memory Map ADDESS RANGE Memory Type FE000000 - FFFFFFFF FF000000 - FFFFFFFF Flash SIMM FF800000 - FFFFFFFF a. Mapped to fixed addresses in the SC140 core. Refer to the MSC8101 spec for complete description of the SC140’s Core internal memory map b.
Page 65: Power Rails
Freescale Semiconductor, Inc. 7•1 Power rails. There 3 power buses with the MSC8101: 1)I/O -3.3V nominal 1)Internal Logic - 1.5V nominal. 2)PLL - 1.5V nominal. and there are 3 power buses on the MSC8101ADS: 1)5V bus 2)3.3V bus logic FIGURE 7-1 ADS Power Scheme ADS Logic &...
Page 66: 5V Bus
Freescale Semiconductor, Inc. cation Maximum Current Consumption" TABLE 7-1. Off-Board Application Maximum Current Consumption To protect on-board devices against supply spikes, decoupling capacitors (typically 0.1µF) are provided between the devices’ power leads and GND, located as close as possible to the power leads, while 47 µF bulk capacitors are spread around.
Page 67 Freescale Semiconductor, Inc. APPENDIX A - MSC8101 Bill of Material MSC8101ADS RevB User’s Manual MOTOROLA A-67 For More Information On This Product, Go to: www.freescale.com...
Page 68: Bom
Freescale Semiconductor, Inc. A•1 In this section the MSC8101ADS’s RevB bill of material is listed according to their reference des- ignation TABLE A-1. MSC8101ADS Bill Of Material Reference Designation C1,C2,C3,C4,C6,C7,C8,C9,C14, Capacitor 0.1µF, 16V, 10%, SMD C15,C20,C21,C23,C24,C26,C27, 0603, Ceramic C28,C29,C30,C31,C33,C34,C35, C36,C37,C39,C40,C41,C42,C43, C44,C45,C48,C49,C50,C51,C53, C54,C55,C56,C57,C61,C62,C63, C64,C66,C67,C68,C69,C72,C73,...
Page 69 Freescale Semiconductor, Inc. TABLE A-1. MSC8101ADS Bill Of Material Reference Designation C117 Capacitor 10uF, 10V, 10% SMD Size A, C185,C186 Capacitor 47pF, 50V, 5% COG SMD Size 1206, Ceramic C188,C191,C204 Capacitor 1µF, 16V, 10%, X7R SMD Size 1206, Ceramic C209 Capacitor 100uF, 16V, 10% SMD Size D ,Tantalum C22,C202...
Page 70 Freescale Semiconductor, Inc. TABLE A-1. MSC8101ADS Bill Of Material Reference Designation Connector 8 pin, RJ45 Receptacle, Shielded, 90 P15,P16 Connector SMB Straight PCB Jack P17,P18 Connector 6 pin, double, RJ45 Receptacle, Shielded, 90 P19,P21,P24 Connector Stereo Phone Jack P20,P22,P23,P25 Connector RCA Jack, Straight Connector 3 pin, Power, Straight, with false insertion protection Connector 3 pin, Power Plug...
Page 71 Freescale Semiconductor, Inc. TABLE A-1. MSC8101ADS Bill Of Material Reference Designation Resistor 1 KΩ, 1%, SMD 0603, 0.1W R34,R39,R48,R54,R63,R66, R67,R72,R73,R93,R96,R103, R108,R111,R119,R121,R209 Resistor 1.5KΩ, 1%, SMD 1206, R41,R42,R43,R44,R45,R46,R47 1/4W R49,R129,R135,R167 Resistor 22.1Ω, 1% SMD 0603, 0.1W R50,R132,R229 Resistor 2.2KΩ 1% SMD 1206, 1/4W Resistor 0 Ω, SMD 1206, 1/4W R60,R157 Resistor 51.1 Ω, 1%, SMD 0603,...
Page 72 Freescale Semiconductor, Inc. TABLE A-1. MSC8101ADS Bill Of Material Reference Designation R200 Resistor 8.45 KΩ, 1% SMD 1206, 1/4W R201,R220 Resistor 5KΩ, 5% SMD 1206, 1/4W Resistor 2.7 Ω, 1% SMD 1206, 1/4W R97,R102,R105,R116,R126 Resistor 750 Ω, 1% SMD 1206, 1/4W R211 R222 Resistor 47.5 KΩ...
Page 73 Freescale Semiconductor, Inc. TABLE A-1. MSC8101ADS Bill Of Material Reference Designation EPM7256A Macrocell, 7 nsec propagation delay, EEPROM Programmable Logic Device, 144-pin TQFP U3,U4,U11,U13,U21,U22,U23,U24, Quad CMOS buffer with individual Output Enable. TSSOP pkg. U39,U5 Low Voltage, CMOS, 5V Tolerant, 16-bit Buffer with Output Enable, 48- pin Plastic TSSOP, Case 1201-01 Fast Ethernet Transceiver.
Page 74 Freescale Semiconductor, Inc. TABLE A-1. MSC8101ADS Bill Of Material Reference Designation Clock Generator 1.544MHz, 3.3V Supply, 4-pin Socket 8-pin SMD Quad E1/T1 Framer PEB22554-HT- V1.3, 144-pin QFP pkg. Eight Transformers for Quad E1/T1 Ports, SMD U29,U30,U32 Rail-to-Rail Output Audio Amp., SMD, SO-8 24-Bit Audio Stereo Codec CS4221, 28-pin SSOP...
Page 75 Freescale Semiconductor, Inc. MSC8101ADS RevB User’s Manual MOTOROLA A-75 For More Information On This Product, Go to: www.freescale.com...
Page 76 Freescale Semiconductor, Inc. APPENDIX B - Support Information MSC8101ADS RevB User’s Manual MOTOROLA B-75 For More Information On This Product, Go to: www.freescale.com...
Page 77: Interconnect Signals
Freescale Semiconductor, Inc. In this chapter all information needed for support, maintenance and connectivity to the MSC8101ADS is provided. B•1 Interconnect Signals The MSC8101ADS interconnects with external devices via the following set of connectors: P1 - System Expansion P2 - CPM Expansion P3 - Altera’s In System Programming (ISP) P4 - Host I/F P5, P7, P8, P9, P10, P13, P14 - Logic Analyzer MICTOR Connectors...
Page 78: Table B1-2
Freescale Semiconductor, Inc. Expansion - Interconnect Signals" TABLE B1-2. P1 - System Expansion - Interconnect Signals Pin No. Signal Name EXPA16 EXPA17 EXPA18 EXPA19 EXPA20 EXPA21 EXPA22 EXPA23 EXPA24 EXPA25 EXPA26 EXPA27 EXPA28 EXPA29 EXPA30 EXPA31 N.C. EXPDVALb N.C. MSC8101ADS RevB User’s Manual MOTOROLA For More Information On This Product, below:...
Page 79 Freescale Semiconductor, Inc. TABLE B1-2. P1 - System Expansion - Interconnect Signals Pin No. Signal Name Attribute TSTAT0 I,P.U. TSTAT1 TSTAT2 TSTAT3 TSTAT4 TSTAT5 TSTAT6 TSTAT7 TOOLREV0 I,P.U. TOOLREV1 TOOLREV2 TOOLREV3 EXTOLI0 I,P.U. EXTOLI1 EXTOLI2 EXTOLI3 PORSTb I/O,P.U. MSC8101ADS RevB User’s Manual B-78 For More Information On This Product, Description...
Page 80 Freescale Semiconductor, Inc. TABLE B1-2. P1 - System Expansion - Interconnect Signals Pin No. Signal Name V3.3 N.C. CLKX BTOLCS1b BTOLCS2b ATMENb ATMRSTb FETHRSTb HRESETb MSC8101ADS RevB User’s Manual MOTOROLA For More Information On This Product, Attribute 3.3V Power Out. These lines are connected to the main 3.3V plane of the MSC8101ADS, this, to provide 3.3V power where necessary for external tool connected.
Page 81 Freescale Semiconductor, Inc. TABLE B1-2. P1 - System Expansion - Interconnect Signals Pin No. Signal Name Attribute IRQ6b I,P.U. IRQ7b I.P.U. EXPD0 I/O, T.S. EXPD1 EXPD2 EXPD3 EXPD4 EXPD5 EXPD6 EXPD7 EXPD8 EXPD9 EXPD10 EXPD11 EXPD12 EXPD13 EXPD14 EXPD15 IRQ4b I.P.U.
Page 82 Freescale Semiconductor, Inc. TABLE B1-2. P1 - System Expansion - Interconnect Signals Pin No. Signal Name N.C. EXPWE0b EXPWE1b EXPGL0b EXPGL1b EXPGL2b EXPGL3b EXPGL4b EXPGL5b V3.3 EXPCTL0 MSC8101ADS RevB User’s Manual MOTOROLA For More Information On This Product, Attribute Not Connected Digital Ground.
Page 83: Msc8101Ads's P2 - Cpm Expansion Connector
Freescale Semiconductor, Inc. TABLE B1-2. P1 - System Expansion - Interconnect Signals Pin No. Signal Name Attribute a. MS Bit. B•1•2 MSC8101ADS’s P2 - CPM Expansion Connector P4 is a 128 pin, 90 , DIN 41612 connector, which allows for convenient expansion of the MPC8101’s serial and host ports.
Page 84 Freescale Semiconductor, Inc. TABLE B1-3. P2 - CPM Expansion - Interconnect Signals Pin No. Signal Name SPISELb(PD19) SPICLK(PD18) SPIMOSI(PD17) A16-A20 N.C. HCS2 HCS1 HRDRW HWRDS A26-A28 N.C. ATRCKDIS HOSTPD A31-A32 ATMTXENb (PA31) MSC8101ADS RevB User’s Manual MOTOROLA For More Information On This Product, Attribute I/O, T.S.
Page 85 Freescale Semiconductor, Inc. TABLE B1-3. P2 - CPM Expansion - Interconnect Signals Pin No. Signal Name Attribute ATMTCAb (PA30) I/O, T.S. ATMTSOC (PA29) I/O, T.S. ATMRXENb (PA28) I/O, T.S. ATMRSOC (PA27) I/O, T.S. ATMRCA (PA26) I/O, T.S. ATMTXD0 (PA25) I/O, T.S. ATMTXD1 (PA24) ATMTXD2 (PA23) ATMTXD3 (PA22)
Page 86 Freescale Semiconductor, Inc. TABLE B1-3. P2 - CPM Expansion - Interconnect Signals Pin No. Signal Name ATMRXD7 (PA17) ATMRXD6 (PA16) ATMRXD5 (PA15) ATMRXD4 (PA14) ATMRXD3 (PA13) ATMRXD2 (PA12) ATMRXD1 (PA11) ATMRXD0 (PA10) L1TXD(PA9) L1RXD(PA8) L1TSYNC(PA7) L1RXSYNC(PA6) HD14 HD15 FETHTXER (PB31) FETHRXDV (PB30) MSC8101ADS RevB User’s Manual MOTOROLA...
Page 87 Freescale Semiconductor, Inc. TABLE B1-3. P2 - CPM Expansion - Interconnect Signals Pin No. Signal Name Attribute FETHTXEN (PB29) I/O, T.S. FETHRXER (PB28) I/O, T.S. FETHCOL (PB27) I/O, T.S. FETHCRS (PB26) I/O, T.S. FETHTXD3 (PB25) I/O, T.S. FETHTXD2 (PB24) FETHTXD1 (PB23) FETHTXD0 (PB22) FETHRXD0 (PB21) I/O, T.S.
Page 88 Freescale Semiconductor, Inc. TABLE B1-3. P2 - CPM Expansion - Interconnect Signals Pin No. Signal Name HD10 HD11 HD12 HD13 ATMRCLK CLK1(PC31) PC30 FETHRXCK (PC29) FETHTXCK (PC28) MSC8101ADS RevB User’s Manual MOTOROLA For More Information On This Product, Attribute I/O, T.S. Host Interface Bidirectional Data Port D0-D13.
Page 89 Freescale Semiconductor, Inc. TABLE B1-3. P2 - CPM Expansion - Interconnect Signals Pin No. Signal Name Attribute CLK5 (PC27) I/O, T.S. ATMFCLK (PC26) I/O, T.S. DACK2b(PC25) I/O, T.S. DREQ2b(PC24) I/O, T.S. DACK1b(PC23) I/O, T.S. DREQ1b(PC22) I/O, T.S. N.C. PC15 I/O, T.S. SCC1CDb (PC14) I/O, T.S.
Page 90 Freescale Semiconductor, Inc. TABLE B1-3. P2 - CPM Expansion - Interconnect Signals Pin No. Signal Name FETHMDIO (PC12) HREQTRQ N.C. HRRQACK SMCTX1(PC5) SMCRX1(PC4) a. The functions in parenthesis, are MSC8101’s parallel I/Os. b. Normally connected to ATMTFCLK on the ADS. c.
Page 91: P3 - Altera's In System Programming (Isp)
Freescale Semiconductor, Inc. B•1•3 P3 - Altera’s In System Programming (ISP) This is a 10 pin generic 0.100" pitch header connector, providing In System Programming capabil- ity for Altera CPLD devices made programmable logic on board. The pinout of P3 is shown in TABLE B1-4.
Page 92 Freescale Semiconductor, Inc. TABLE B1-5. P4 - Host Interface Connector - Interconnect Signals Pin No. Signal Name HD10 HD11 HD12 HD13 HD14 HD15 HCS1 HCS2 HACK HREQ MSC8101ADS RevB User’s Manual MOTOROLA For More Information On This Product, Attribute I/O, T.S. Host Interface Bidirectional Data Port HD(0:15).
Page 93: P5, P7, P8, P9, P10, P13, P14 - Logic Analyzer Connectors
Freescale Semiconductor, Inc. TABLE B1-5. P4 - Host Interface Connector - Interconnect Signals Pin No. Signal Name Attribute HRESETb I/O, P.U PORSTb I/O, P.U N.C. B•1•5 P5, P7, P8, P9, P10, P13, P14 - Logic Analyzer Connectors These are 38 pin, SMT, high density, matched impedance connector made by AMP. They contain all MSC8101 signals unbuffered.
Page 94: P12 - Ethernet Port Connector
Freescale Semiconductor, Inc. TABLE B1-6. P6 - JTAG/ONCE Connector - Interconnect Signals Pin No. Signal Name N.C. TRSTb B•1•7 P12 - Ethernet Port Connector The Ethernet connector on the MSC8101ADS - P12, is a Twisted-Pair (10-Base-T) compatible connector. It is implemented with a 90 TABLE B1-8.
Page 95: P19,P21,P24 - Stereo Phone Jack Connectors
Freescale Semiconductor, Inc. Connectors Interconnect Signals" below TABLE B1-8. P17,P18 - T1/E1 Line Connectors Interconnect Signals Signal Name RX1+ Twisted-Pair Receive Data 1-ch. positive input from the MSC8101ADS. RX1- Twisted-Pair Transmit Data 1-ch. positive input from the MSC8101ADS. Digital Ground plane. TX1+ Twisted-Pair Transmit Data 1-ch.
Page 96: P26 - 5V Power Supply Connectors
Freescale Semiconductor, Inc. B•1•12 P26 - 5V Power Supply Connectors FIGURE 3-4, "P26: +5V Power Connector" on page 21 B•1•13 P27A,B - RS232 Ports’ Connectors The RS232 ports’ connectors - PA3 and PB3 are 9 pin, 90 signals of which are presented in "P27B Interconnect Signals"...
Page 97 Freescale Semiconductor, Inc. MSC8101ADS RevB User’s Manual MOTOROLA B-96 For More Information On This Product, Go to: www.freescale.com...
Page 98 Freescale Semiconductor, Inc. APPENDIX C - Program Information MSC8101ADS RevB User’s Manual MOTOROLA C-97 For More Information On This Product, Go to: www.freescale.com...
Page 99 Freescale Semiconductor, Inc. The MSC8101 has one programmable logic device - Altera CPLD, serving control and stasus function on the ADS. It implemented an U2 EPM7128ATC144-7. The design is done in AHDL program format and is listed below: MSC8101ADS RevB User’s Manual C-98 For More Information On This Product, Go to: www.freescale.com...
Page 100: Logic Equations
Logic Equations C•1•1 First Include File %*********************bcsrA.inc ************************************% TITLE “MSC8101 ADS Board Control and Status Register.”; Written by Yehuda Palchan - November , 1999 This file defines the Constant declarations used by the BCSR %*******************************************************************% -- The reserved lines are granted with ACTIVE/NOT ACTIVE states.
Page 101: Second Include File
Freescale Semiconductor, Inc. C•1•2 Second Include file %*********************ResetEnsure.tdf ******************************% TITLE “MSC8101 ADS Board Control and Status Register.”; Written by Yehuda Palchan - February , 2000 This file defines the Reset Ensure State Machine %*******************************************************************% SubDesign Reset_Ensure Clk: INPUT; Reset: INPUT;...
Page 102: Main File
Freescale Semiconductor, Inc. C•1•3 Main File %*********************bcsr.tdf ***************************************% TITLE “MSC8101ADS Board Control and Status Register.”; Written by Dragilev Lev, MSIL Rev B Version Release 1.0 31/10/2002 This file declares the BCSR registers and their functions It also controlls the Codec, Flash, RS232, T1/E1 Framer,Host Interface and ATM devices.
Page 103 Freescale Semiconductor, Inc. ********** BCSR3 Power On Default Assignments ******* ***************************************************** CONSTANT EE0_PON_DEFAULT = EE0_ACTIVE; CONSTANT EE1_PON_DEFAULT = EE1_ACTIVE; CONSTANT EE2_PON_DEFAULT = EE2_ACTIVE; CONSTANT EE3_PON_DEFAULT = EE3_ACTIVE; CONSTANT EE4_PON_DEFAULT = EE4_ACTIVE; CONSTANT EE5_PON_DEFAULT = EE5_ACTIVE; CONSTANT EED_PON_DEFAULT = EED_ACTIVE; CONSTANT RSV3_7_PON_DEFAULT = RSV3_7_NACTIVE;...
Page 104 Freescale Semiconductor, Inc. CONSTANT TCPC_DEFAULT0 = 1; CONSTANT TCPC_DEFAULT1 = 0; CONSTANT BC1PC_DEFAULT0 = 0; CONSTANT BC1PC_DEFAULT1 = 0; CONSTANT RSVHR26 = 0; -- CONSTANT DLLDIS_DEFAULT= 0; CONSTANT RSVHR31 = 0; SUBDESIGN bcsr clock, ExtClk, CS1~, W_R~, A[27..29], A7,A8 -- Flash address : INPUT;...
Page 105 Freescale Semiconductor, Inc. SBOOTEN_OUT~, -- Enable Boot to serial EEPROM F_CS1~, F_CS2~, F_CS3~, F_CS4~, -- External FLASH memory chip-selects 1,2,3,4 SPARE1 : OUTPUT; %****************************% % Host Interface Definition %****************************% HDI_EN~, -- Host Enable to Buffer HRRQ_EN~, -- Host Recieve Request Enable HACK_EN~, -- Host Acknowledge Enable HDI_WR...
Page 106 Freescale Semiconductor, Inc. D[0..7] : BIDIR; DUMMY : BIDIR; VARIABLE Bcsr0[0..SIZE0], Bcsr1[0..SIZE1], Bcsr4[2..SIZE4], -- BCSR4 is utilized for MODCK reconfig - Service Register 1 Bcsr5[0..SIZE5], -- BCSR5 is utilized to program synthesizer - Service Register 2 Bcsr6[0..SIZE6], -- BCSR6 is utilized to program synthesizer - Service Register 3 WE0Spare, HOST_EN, SyncHardReset,...
Page 107 Freescale Semiconductor, Inc. SCND_CFG_BYTE_READ, THIRD_CFG_BYTE_READ, FOURTH_CFG_BYTE_READ, F_PD[4..1], T1_EN_OUT_NODE, T234_EN_OUT_NODE, CODECEN_OUT_NODE, FETHIEN_OUT_NODE, CONF_ADD[0..1],-- CONFIGURATION ADDRESS CFG_BYTE0[0..7], CFG_BYTE1[0..7], CFG_BYTE2[0..7], CFG_BYTE3[0..7], END_OF_FLASH_READ,-- “1” if DSP has ended Flash reading END_OF_ATM_READ,-- “1” if DSP has ended ATM reading DATA_HOLD_END, -- “1” if Data_Hold counter has reached its limit EE0_HOLD_END, -- “1”...
Page 108 Freescale Semiconductor, Inc. * BCSR3 ********************************************************************************% EE0_node, EE1_node, EE2_node, EE3_node, EE4_node, EE5_node, EED_node, RSV3_7, %******************************************************************************** BCSR4 - Write Register ********************************************************************************% -- PORESET pulse start when write high RSV4_1, -- Should be zero for produce PORESET pulse MODCK4r, -- Registered MODCK4 MODCK5r, -- Registered MODCK5 MODCK6r,...
Page 109 Freescale Semiconductor, Inc. SoftReset~, HRD_HRWd BEGIN DEFAULTS Data_Buff[].oe = GND; -- Data Bus Output disable DivEn.clrn = VCC; END DEFAULTS; RESETi = !HARD_RESET_ACTIVE~ or REGULAR_POWER_ON_RESET; HOSTCSP,HOSTRQAC,HOSTTRI, T1_1EN~,T1_234EN~,FrmRst~,SIGNAL_LAMP_0~,SIGNAL_LAMP_1~) = Bcsr0[0..SIZE0].q; SBOOT_EN~,CODEC_EN~,ATM_EN~,ATM_RST~,FETHIEN~,FETH_RST~,RS232EN_1~,RS232EN_2~) = Bcsr1[0..SIZE1].q; EE0_node,EE1_node,EE2_node,EE3_node,EE4_node,EE5_node,EED_node,RSV3_7) = (EE[0..5],EED,GND); MODCK4r,MODCK5r,MODCK6r,MODCK1r,MODCK2r,MODCK3r) = Bcsr4[2..SIZE4].q; ***************************************************** ******* Power On Defaults Value Generation ********* ***************************************************** ------------------...
Page 110 Freescale Semiconductor, Inc. ATM_RST_PON_DEFAULT,FETHIEN_PON_DEFAULT,FETH_RST_PON_DEFAULT, ------------------ BCSR3 ------------------ BCSR3_PON_CONST[] = (EE0_PON_DEFAULT,EE1_PON_DEFAULT,EE2_PON_DEFAULT, FOR i IN 0 to SIZE0 GENERATE IF(BCSR0_PON_CONST[i]) THEN ELSE END IF; END GENERATE; FOR i IN 0 to SIZE1 GENERATE IF(BCSR1_PON_CONST[i]) THEN BCSR1_PON_DEF[i] = VCC; ELSE BCSR1_PON_DEF[i] = GND; END IF;...
Page 111 Freescale Semiconductor, Inc. WE0Spare.clk = GLOBAL(clock); SyncTEA.d = VCC; -- for optional use TEA~ = OPNDRN(SyncTEA.q); FlashOE.d= VCC; BPOE~= OPNDRN(FlashOE); PSDVAL~ = OPNDRN(VCC); WE0Spare.d= VCC; WE0 = OPNDRN(WE0Spare); %************************************* EE PINS *************************************% EE0_HOLD.aclr = !HRESET~; EE0_HOLD_END = (EE0_HOLD.q[] == EE0_HOLD_VALUE); -- terminal count IF(EE0_HOLD_END &...
Page 112 Freescale Semiconductor, Inc. ELSE HRD_SHIFT.aclr = GND; END IF; HRD_SHIFT.shiftin= HRD_HRW;--LOAD SHIFT REGISTER HRD_HRWd= HRD_SHIFT.shiftout;--READ SHIFT REGISTER --HDI_WR = (((!HDDS and !HRD_HRW) or -- (!((!HDDS and !HRD_HRW) or (HDDS and HRD_HRWd)) and !HDSP); --ASSIGN HOST-Write NODE -- HDI_WR = ~(HCS1 * HCS2) * (HDDS ? (HDSP ^ HRD_HRW) : ~HRD_HRW) IF (HDDS) THEN -- Double Strobe Mode IF (!HDSP) THEN...
Page 113 Freescale Semiconductor, Inc. END IF; ************************* ** BCSR1 Write Operation ** ************************* IF (RESETi) THEN Bcsr1[].d = BCSR1_PON_DEF[]; ELSIF (MPC_WRITE_BCSR_1) THEN Bcsr1[0..SIZE1].d = D[0..SIZE1]; ELSE Bcsr1[].d = Bcsr1[].q; END IF; ********************************************* ** BCSR4 Service Register 1 Write Operation ** ********************************************* PRST_Ensure.aclr = PRST~;...
Page 114 Freescale Semiconductor, Inc. -- Assign Configuration Word: FROM_FLASH_CNFG_WORD = (F_CFG_EN~ == GND); FROM_HOST_CNFG_WORD = (HOSTCFG~ == GND); CFG_BYTE0[0..7]= (EARB_DEFAULT,EXMC_DEFAULT,IRQ7INT~_DEFAULT,EBM_DEFAULT,BPS_DEFAULT0,BPS_DEFAULT1, SCDIS_DEFAULT,ISPS_DEFAULT); (IRPC_DEFAULT0,IRPC_DEFAULT1,DPPC_DEFAULT1,DPPC_DEFAULT0,NMIOUT_DEFAULT,ISB_DAFAULT0, ISB_DAFAULT1,ISB_DAFAULT2); CFG_BYTE2[0..7]= (RSVHR16,BBD_DEFAULT,RSVHR18,RSVHR19,RSVHR20,RSVHR21,TCPC_DEFAULT0,TCPC_DEFAULT1); CFG_BYTE3[0..7]= (BC1PC_DEFAULT0,BC1PC_DEFAULT1,RSVHR26,DLLDIS,MODCK4r,MODCK5r,MODCK6r,RSVHR31); CONF_ADD[]=(A27,A28); FIRST_CFG_BYTE_READ = (!F_Cs0~ & !HARD_RESET_ACTIVE~ & (CONF_ADD[] == 0) & !FROM_FLASH_CNFG_WORD & !FROM_HOST_CNFG_WORD & !W_R~); SCND_CFG_BYTE_READ = (!F_Cs0~ &...
Page 115 Freescale Semiconductor, Inc. (EE0_node,EE1_node,EE2_node,EE3_node,EE4_node,EE5_node,EED_node ELSIF (MPC_READ_BCSR_4) THEN Data_Buff[].oe = VCC; Data_Buff[0..SIZE4].in = ((!F_CFG_EN~),DLLDIS,Bcsr4[2..SIZE4].q); ELSIF (MPC_READ_BCSR_5) THEN Data_Buff[].oe = VCC; Data_Buff[0..SIZE5].in = Bcsr5[0..SIZE5].q; ELSIF (MPC_READ_BCSR_6) THEN Data_Buff[].oe = VCC; Data_Buff[0..SIZE6].in = Bcsr6[0..SIZE6].q; -- Assign Default Configuration Word onto Data Bus: ELSIF (FIRST_CFG_BYTE_READ) THEN Data_Buff[].oe = VCC;...
Page 116 Freescale Semiconductor, Inc. * Buffers Enable & ATM Chip Select ****************************************************************************** DATA_HOLD_END = (DATA_HOLD.q[] == DATA_HOLD_VALUE); -- terminal count IF(DATA_HOLD_END & DSyncHardReset) THEN DATA_HOLD.cnt_en = GND; -- Disable count after term value ELSE END IF; END_OF_FLASH_READ = !PSDVal~ & !F_CS0~ & !W_R~ & DSyncHardReset; -- end of flash read cycle. END_OF_ATM_READ = !PSDVAL~ &...
Page 117 Freescale Semiconductor, Inc. END IF; T1_EN_OUT~ = T1_EN_OUT_NODE; T1_1LED = OPNDRN(T1_EN_OUT_NODE); T234_EN_OUT~ = OPNDRN(T234_EN_OUT_NODE); FETHIEN_OUT~ = FETHIEN_OUT_NODE; CODECEN_OUT~ = OPNDRN(CODECEN_OUT_NODE); DUMMY = OPNDRN(VCC); -- Test Workaround ****************************************************************************** * ATM ENABLE AND RESET LOGIC (Use BCSR1) ****************************************************************************** IF (ATM_EN~ == ATM_ENABLED) THEN ATM_EN_OUT~ = GND; ELSE END IF;...
Page 118 Freescale Semiconductor, Inc. SM73228X = (F_PD[] == 2);-- 8MByte -- Declare 4 Flash Banks: FLASH_BANK1 = ( SM73228X # (SM73248X & !A8) # ( SM73288X & !A7 & !A8)) ; FLASH_BANK2 = ((SM73248X & A8) # (SM73288X & !A7 & A8)) ; FLASH_BANK3 = (A7 &...
Page 119 Freescale Semiconductor, Inc. with default MODCK setting from DIP-Switch PONRESET pulse resets while WD. Implemented as ripple counter with 30 stages -- WDEn.s = GND; WDEn.r = GND; -- WDEn.prn = !(MPC_WRITE_BCSR_4 & (D[0..1] == B”10”)); -- Preset to FF when write b’10 bit to BCSR4 -- WDEn.clrn = !END_OF_WD_TIMER &...

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