Diagrams - Sony PCM-D50 Service Manual

PCM-D50
THIS NOTE IS COMMON FOR PRINTED WIRING BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is printed in each block.)
For Printed Wiring Boards.
Note:
• X : Parts extracted from the component side.
• : Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
Caution:
Pattern face side: Parts on the pattern face side seen from
(SIDE B) the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(SIDE A) the parts face are indicated.
• Lead layouts
Lead layout of conventional IC
18
SECTION 4

DIAGRAMS

surface
CSP (Chip Size Package)
For Schematic Diagrams.
Note:
• All capacitors are in μF unless otherwise noted. (p: pF)
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ω and
1 /
4
specifi ed.
• : internal component.
f
• C : panel designation.
Note:
The components identi-
fi ed by mark 0 or dotted
line with mark 0 are criti-
cal for safety.
Replace only with part
number specifi ed.
• A : B+ Line.
• B : B– Line.
• Power voltage is dc 6.0V and fed with regulated dc power
supply from battery terminal.
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
no mark : PB
[ ] : REC
: Impossible to measure
*
• Voltages are taken with a VOM (Input impedance 10 MΩ).
Voltage variations may be noted due to normal production
tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal production
tolerances.
• Circled numbers refer to waveforms.
• Signal path.
: REC (DIGITAL)
c
: REC (ANALOG)
L
: PB (DIGITAL)
J
: PB (ANALOG)
F
• The voltage and waveform of CSP (chip size package)
cannot be measured, because its lead layout is different
from that of conventional IC.
W or less unless otherwise
Note:
Les composants identifi és
par une marque 0 sont
critiques pour la sécurité.
Ne les remplacer que par
une piéce portant le nu-
méro spécifi é.