Figure 8-59. Memory Interface Circuit (Pc000353A01) - Motorola APX 1000 Detailed Service Manual

8-126
DDR INTERFACE
U6302M6
D9
SDCLKX
C9
SDCLK
H12
SDCLK_EN
H8
NSWE
B3
SBANK_0
C3
SBANK_1
D6 H7
SDATA_0 CONTROL NSRAS
C6 B4
SDATA_1 NSCAS
C5 G8
SDATA_2 CS_SDRAM
D7 D10
SDATA_3 NSDQMU
D5 C8
SDATA_4 NSDQML
C7 C14
SDATA_5 DSQ_H
C4 D4
SDATA_6 DSQ_L
D8 A2
SDATA_7 SADD_0
C10 B2
SDATA_8 DATA SADD_1
D14 B6
SDATA_9 SADD_2
D11 A1
SDATA_10 SADD_3
C13 G10
SDATA_11 SADD_4
C11 B9
SDATA_12 SADD_5
D13 G12
SDATA_13 SADD_6
D12 G11
SDATA_14 ADDRESS SADD_7
C12 G9
SDATA_15 SADD_8
B12
SADD_9
B8
SADD_10
H10
SADD_11
H9
SADD_12
H11
SADD_13
DDR_DATA<17..0>
MMC INTERFACE
F2_TIMER_OUT
U6302M6
V11
MMC1_CLK
M15
MMC1_CLKIN
P11
MMC1_CMD
P19
MMC1_CMDDIR
P20
MMC1_DATDIR0
P18
OPTION CARD INTF MMC1_DATDIR1
M14
MMC1_DATDIR2
R18
MMC1_DATDIR3
R11
MMC1_DAT0
V10
MMC1_DAT1
W10
MMC1_DAT2
W11
MMC1_DAT3
Y10
MMC2_CLK
Y8
MMC2_CMD
V9
MMC2_CMDDIR
V5
MMC2_DATDIR0
MEMORY CARD INTF
W19
MMC2_DATDIR1
W8
MMC2_DAT0
V8
MMC2_DAT1
W15
MMC2_DAT2
R10
MMC2_DAT3

Figure 8-59. Memory Interface Circuit (PC000353A01)

R6301M6
TP6307M6
TP6308M6
DDR_CLKX_1
DDR_CLK_1 G2
CK
DDR_CLKE G3
CK*
DDR_WE G1
CKE
DDR_BANK0 DDR_CS H7
CS
DDR_BANK1 DDR_RAS G9
RAS
DDR_RAS DDR_CAS
G8
CAS
DDR_CAS DDR_WE G7
WE
DDR_CS DDR_CRTL<6..0> DDR_UDM F2
UDM
DDR_UDM DDR_LDM F8
LDM
DDR_LDM DDR_BANK0 H8
BA0
DDR_DQSH H9
BA1
DDR_DQSL J8
A0
J9
A1
DDR_ADDR<2> K7
A2
DDR_ADDR<3> K8
A3
DDR_ADDR<4> K2
A4
DDR_ADDR<5> K3
A5
DDR_ADDR<6> J1
A6
DDR_ADDR<7> J2
A7
DDR_ADDR<8> J3
A8
DDR_ADDR<9> H1
A9
DDR_ADDR<10> J7
A10_AP
DDR_ADDR<11> H2
A11
DDR_ADDR<12> H3
A12
F7
A13
D9
TEST
DDR_ADDR<13..0>
1
TP6301M6
AVR_STATUS_1.8V
OUT
Schematics, Boards Overlays, and Parts Lists: Transceiver (RF) Boards: UHF1 (84012313002 / PC000353A01)
1
TP6304M6
U6301M6
1
TP6303M6
E2 DDR_DQSH
UDQS
E8 DDR_DQSL
LDQS
A8 DDR_DATA<0>
DQ0
B7 DDR_DATA<1>
DQ1
DDR_DATA<2>
B8
DQ2
C7 DDR_DATA<3>
DQ3
C8 DDR_DATA<4>
DQ4
D7 DDR_DATA<5>
DQ5
D8 DDR_DATA<6>
DQ6
E7 DDR_DATA<7>
DQ7
E3 DDR_DATA<8>
DQ8
D2 DDR_DATA<9>
DQ9
D3 DDR_DATA<10>
DQ10
C2 DDR_DATA<11>
DQ11
C3 DDR_DATA<12>
DQ12
B2 DDR_DATA<13>
DQ13
B3 DDR_DATA<14> PA_SHTDN
DQ14
A2
DDR_DATA<15>
DQ15
F3
NC NC
R6492M6
FLASH INTERFACE
1
TP6305M6
U6302M6
1
TP6306M6
L4
NF_ADV
M7
NFCS_0
M3
NFCS_1
M4
NFCS_2
N8
NFCS_3
U4
NFOE
CONTROL
W1
NFRP
W2
NFWE
V4
NFWP
N4 N3
FDATA_0 FCLK
N2 V2
FDATA_1 FRDY
N7 J8
FDATA_2 FADD_1
P2 D3
FDATA_3 FADD_2
P4 C1
FDATA_4 FADD_3
P7 E4
FDATA_5 FADD_4
R2 D2
FDATA_6 FADD_5
R3 F4
FDATA_7 FADD_6
R4 E3
FDATA_8 DATA FADD_7
T2 J7
FDATA_9 FADD_8
T3 F3
FDATA_10 FADD_9
P8
G4
FDATA_11 FADD_10
U1 G3
FDATA_12 FADD_11
U3 G2
FDATA_13 FADD_12
T4 K8
FDATA_14 ADDRESS FADD_13
V3 H4
FDATA_15 FADD_14
H3
FADD_15
K7
FADD_16
J2
FADD_17
J4
FADD_18
J3
FADD_19
F2
FADD_20
L8
FADD_21
K4
FADD_22
K3
FADD_23
L7
FADD_24
E1
FADD_25
FLASH_DATA<15..0>
CHANGES MADE
ADDED PA_SHTDN TO PORT M7 & R6492
R6316M6
FLASH_CTRL<8..0>
R6304M6
FLASH_RDY
R6306M6
R6310M6
R6314M6
R6311M6
E6
CLK
B4
CE
FLASH_OE_A
F8
OE
G8
WE
TP6302M6 1 D4
R6313M6 RST
C6
WP
R6312M6 F6
ADV
A1
A1
B1
A2
C1
A3
D1
A4
D2
A5
A2
A6
C2
A7
A3
A8
B3
A9
C3
A10
D3
A11
C4
A12
A5
A13
B5
A14
C5
A15
D7
A16
D8
A17
A7
A18
B7
A19
C7
A20
C8
A21
A8
A22
G1
A23
H8
A24
B6
A25_512M
B8
A26_1G
NC
FLASH_ADDR<25..1>
V_FLASH
U6304M6
F7
WAIT
F2
DQ0
E2
DQ1
G3
DQ2
E4
DQ3
E5
DQ4
G5
DQ5
G6
DQ6
H7
DQ7
E1
DQ8
E3
DQ9
F3
DQ10
F4
DQ11
F5
DQ12
H5
DQ13
G7
DQ14
E7
DQ15
E8
RFU1
NC
F1
RFU2
NC
G2
RFU3
NC
H1
RFU4
NC