Motorola ColdFire MCF5281 User Manual page 805

(IAUR/IALR), 17-38
descriptor individual
(IAUR/IALR), 17-37
FIFO receive bound (FRBR), 17-41
FIFO receive start (FRSR), 17-42
FIFO transmit FIFO watermark (TFWR), 17-40
interrupt event (EIR), 17-23
interrupt mask (EIMR), 17-26
MIB control (MIBC), 17-32
MII management frame (MMFR), 17-29
MII speed control (MSCR), 17-31
opcode/pause duration (OPD), 17-37
physical address low/high (PALR, PAUR), 17-35
receive buffer size (EMRBR), 17-44
receive control (RCR), 17-33
receive descriptor active (RDAR), 17-26
receive descriptor ring start (ERDSR), 17-42
transmit buffer
(ETSDR), 17-43
transmit control (TCR), 17-34
transmit descriptor active (TDAR), 17-27
transmission errors
heartbeat, 17-19
late collision, 17-18
retransmission attempts limit expired, 17-18
transmitter underrun, 17-18
Exceptions
access error, 2-13
address error, 2-14
divide-by-zero, 2-14
exception stack frame, 2-12
format error, 2-16
illegal instruction, 2-14
overview, 2-10
privilege violation, 2-14
program counter, 2-3
reset, 2-16
trace, 2-14
TRAP instruction, 2-16
vector table, 2-11
External interface module (EIM), seebus
EXTEST instruction, 31-9
F
Fault confinement state (FCS), 25-29
Fault-on-fault halt, 2-16, 29-17
FEC, see Ethernet
FF1 instruction, 2-31
Fill buffer, 4-1
Flash, see ColdFire Flash module
FlexCAN
bit timing, 25-14
CAN system overview, 25-4
error counters, 25-15
MOTOROLA
INDEX
upper/lower address
descriptor ring start
MCF5282 User's Manual
features, 25-1
format frames, 25-5-25-7
IDLE bit, 25-29
initialization sequence, 25-16
interrupts, 25-19
memory map, 25-3
message buffers
BUSY, 25-6
EMPTY, 25-6
FULL, 25-6
handling, 25-10
locking and releasing, 25-12
receive deactivation, 25-11
serial message buffers, 25-11
transmit deactivation, 25-11
NOT ACTIVE, 25-6
overload frames, 25-13
OVERRUN, 25-6
receive
codes, 25-6
error status flag (RXWARN), 25-29
pin configuration control (RXMODE), 25-23
remote frames, 25-12
self-received frames, 25-10
status, 25-29
structure, 25-4
time stamp, 25-13
transmit
codes, 25-6
error status flag (TXWARN), 25-29
length, 25-6
pin configuration control (TXMODE), 25-23
NOTRDY bit, 25-20
operation
auto power save mode, 25-19
bit timing configuration, 25-14
debug mode, 25-17
listen-only mode, 25-13
low-power modes, 7-13, 25-17
overview, 25-1
receive process, 25-9
registers
bit timing, 25-14
control 0-2 (CANCTRLn), 25-22-25-25
error and status (ESTAT), 25-28
free running timer (TIMER), 25-26
interrupt flag (IFLAG), 25-31
interrupt mask (IMASK), 25-30
module configuration (CANMCR), 25-20
prescaler divide (PRESDIV), 25-24
receive error counter (RXECTR), 25-32
receive mask (RXGMASK, RXnMASK), 25-27
transmit error counter (TXECTR), 25-32
SAMP bit, 25-24
transmit process, 25-9
Index-5