Table of Contents
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Overview of Contents
Chapter 1, Programming
features of MVME1X7P single-board computers. It includes memory
maps and a discussion of some general software considerations such as
cache coherency, interrupts, and bus errors.
Chapter 2,
bus/VMEbus interface chip on MVME1X7P boards.
Chapter 3,
peripheral channel controller designed to interface an MC680x0-
compatible local bus to various on-board peripheral devices such as SCSI
and LAN controllers.
Chapter 4, MCECC
(MCECC). On the MVME1X7P boards, it supplies the interface to a 144-
bit wide DRAM memory system.
Appendix A, Summary of
accompanied the introduction of the Petra ASIC on the MVME167P and
MVME177P.
Appendix B, Printer and Serial Port
the printer and serial port interface connections available with the
MVME167P/MVME177P and MVME712 series transition board.
Appendix C, Related
MVME167P and MVME177P.
Comments and Suggestions
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xxii
VMEchip2, describes the VMEchip2 ASIC, the local
PCCchip2, describes the PCCchip2 ASIC. The PCChip2 is a
Functions, describes the ECC DRAM controller ASIC
Documentation, lists all documentation related to the
Motorola Computer Group
Reader Comments DW164
2900 S. Diablo Way
Tempe, Arizona 85282
Issues, describes the board-level hardware
Changes, lists the modifications that
Connections, contains drawings of
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Table of Contents
