Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 135

DRAM: 60ns, CPU: 25MHz, random read/write cycle
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
DRAM: 60ns, CPU: 25MHz, page-mode read/write cycle
BCLK
A[11:0]
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
DRAM: 60ns, CPU: 25MHz, CAS-before-RAS refresh cycle
RPC delay
BCLK
#RAS
#CAS
S1C33L03 PRODUCT PART
APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
RAS cycle CAS cycle
1
ROW #1 COL #1
t
WR data
RAS cycle CAS cycle
1 2
ROW #1 COL #1
RD data
WR data
Fixed Refresh RAS pulse width
1 1
t t
RPC CSR
EPSON
RAS precharge
2 2
RAS
RD data
CAS cycle
2
COL #2
t
RAS
RD data
WR data
RAS precharge
2 2
t
RAS
t
CHR
ROW #2
RAS precharge
2
A-119
A-1
A-ap