Epson CMOS 32-Bit Single Chip Microcomputer S1C33L03 Technical Manual page 131

DRAM: 70ns, CPU: 33MHz, random read/write cycle
BCLK
A[11:0]
t
ASR
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
DRAM: 70ns, CPU: 33MHz, page-mode read/write cycle
RAS cycle
2
BCLK
A[11:0]
ROW #1
#RAS
#CAS
#RD
D[15:0](RD)
#WE
D[15:0](WR)
DRAM: 70ns, CPU: 33MHz, CAS-before-RAS refresh cycle
RPC delay
1
BCLK
#RAS
#CAS
S1C33L03 PRODUCT PART
APPENDIX A <REFERENCE> EXTERNAL DEVICE INTERFACE TIMINGS
RAS cycle CAS cycle
2
ROW #1
t
RAD
t t
RAH ASC
t
RAS
t
RCD
t
RAC
t
OAC
t
WP
t
DS
WR data
CAS cycle
3
COL #1
WR data
Fixed Refresh RAS pulse width
1
t t
RPC CSR
EPSON
t
RC
RAS precharge
3
COL #1
t
CAS
t
AA
t
CAC
RD data
t
DH
t
CAS cycle
COL #2
t
RAS
t
CP
t
ACP
RD data
WR data
RAS precharge
3
t
RAS
t
CHR
2
ROW #2
t
RP
t
OFF
PC
RAS precharge
3 2
RD data
2
A-1
A-ap
A-115