Debug Modes - Epson ARM720T Core Cpu Manual

9: Debugging Your System
9.2.1

Debug modes

You can perform debugging in either of the following modes:
Halt mode
Monitor mode
9.2.2 Examining system state during debugging
In both halt mode and monitor mode, the JTAG-style serial interface enables you to examine
the internal state of the core and the external state of the system while system activity
continues.
In halt mode, this enables instructions to be inserted serially into the core pipeline without
using the external data bus. For example, when in debug state, a
inserted into the instruction pipeline to export the contents of the ARM720T processor
registers. This data can be serially shifted out without affecting the rest of the system. For
more information, see
In monitor mode, the JTAG interface is used to transfer data between the debugger and a
simple monitor program running on the ARM720T core.
For detailed information about the scan chains and the JTAG interface, see
the JTAG interface
9-4
When the system is in halt mode, the core enters
it encounters a breakpoint or a watchpoint. In debug state, the core
is stopped and isolated from the rest of the system. When debug
has completed, the debug host restores the core and system state,
and program execution resumes.
For more information, see
When the system is in monitor mode, the core does not enter debug
state on a breakpoint or watchpoint. Instead, an Instruction Abort
or Data Abort is generated and the core continues to receive and
service interrupts as normal. You can use the abort status register
to establish whether the exception was due to a breakpoint or
watchpoint, or to a genuine memory abort.
For more information, see
Examining the core and the system in debug state
on page 9-17.
Entry into debug state
Monitor mode debugging
EPSON
debug state
on page 9-5.
on page 9-12.
Store Multiple
(STM) can be
on page 9-26.
Scan chains and
ARM720T CORE CPU MANUAL
when