Epson S1D13505 Manuals

Manuals and User Guides for Epson S1D13505. We have 1 Epson S1D13505 manual available for free PDF download: Technical Manual

Epson S1D13505 Technical Manual (556 pages)

Embedded RAMDAC LCD/CRT Controller

Brand: Epson | Category: Computer Hardware | Size: 5.1 MB

Table of Contents

9
Table of Contents

157
- 1 Introduction
  
  165
- 2 Initialization
  
  166
  - Miscellaneous
    169
- 3 Memory Models
  
  170
  - Display Buffer Location
    170
    
    Memory Organization for One Bit-Per-Pixel (2 Colors/Gray Shades)
    170
    
    Memory Organization for Two Bit-Per-Pixel (4 Colors/Gray Shades)
    171
    
    Memory Organization for Four Bit-Per-Pixel (16 Colors/Gray Shades)
    171
    
    Memory Organization for Eight Bit-Per-Pixel (256 Colors/16 Gray Shades)
    172
    
    Memory Organization for Fifteen Bit-Per-Pixel (32768 Colors/16 Gray Shades)
    172
    
    Memory Organization for Sixteen Bit-Per-Pixel (65536 Colors/16 Gray Shades)
    173
- 4 Look-Up Table (LUT)
  
  174
  - Look-Up Table Registers
    174
  - Look-Up Table Organization
    175
- 5 Advanced Techniques
  
  183
  - Virtual Display
    183
    
    Registers
    184
    
    Examples
    185
  - Panning and Scrolling
    185
    
    Registers
    186
    
    Examples
    187
  - Split Screen
    189
    
    Registers
    189
    
    Examples
    191
- 6 LCD Power Sequencing and Power Save Modes
  
  192
  - LCD Power Sequencing
    192
    
    Registers
    192
    
    LCD Power Disable
    193
  - Software Power Save
    194
    
    Registers
    195
  - Hardware Power Save
    196
- 7 Hardware Cursor/Ink Layer
  
  197
  - Introduction
    197
  - Registers
    198
  - Limitations
    200
    
    Updating Hardware Cursor Addresses
    200
    
    Reg[29H] and Reg[2Bh]
    200
    
    Reg [30H]
    200
    
    No Top/Left Clipping on Hardware Cursor
    200
  - Examples
    200
- 8 Swivelview
  
  201
  - Introduction to Swivelview
    201
  - S1D13505 Swivelview
    201
  - Registers
    201
  - Limitations
    202
  - Examples
    203
- 9 CRT Considerations
  
  205
  - Introduction
    205
    
    CRT Only
    205
    
    Simultaneous Display
    205
- 10 Identifying the S1D13505
  
  206
- 11 Hardware Abstraction Layer (HAL)
  
  207
  - Introduction
    207
  - Contents of the HAL_STRUCT
    207
  - Using the HAL Library
    208
  - API for 13505HAL
    208
  - Initialization
    210
    
    General HAL Support
    212
    
    Advanced HAL Functions
    216
    
    Register / Memory Access
    218
    
    Color Manipulation
    221
    
    Drawing
    223
    
    Hardware Cursor
    225
    
    Ink Layer
    229
    
    Power Save
    232
  - Porting LIBSE to a New Target Platform
    232
    
    Building the LIBSE Library for SH3 Target Example
    233
    
    Building the HAL Library for the Target Example
    234
    
    Building a Complete Application for the Target Example
    234
- 12 Sample Code
  
  238
  - Introduction
    238
    
    Sample Code Using the S1D13505 HAL API
    238
    
    Sample Code Without Using the S1D13505 HAL API
    240
    
    Header Files
    249
- Appendix A Supported Panel Values
  
  261
  - Supported Panel Values
    261
Table of Contents

267
- 13505Cfg
  269
- S1D13505 Supported Evaluation Platforms
  269
- Installation
  270
- Usage
  270
- 13505CFG Configuration Tabs
  271
  - General Tab
    271
  - Preferences Tab
    273
  - Memory Tab
    274
  - Clocks Tab
    276
  - Panel Tab
    279
  - CRT/TV Tab
    283
  - Registers Tab
    284
- 13505CFG Menus
  285
  - Open
    285
  - Save
    286
  - Save as
    286
  - Configure Multiple
    287
  - Export
    288
  - Enable Tooltips
    289
  - ERD on the Web
    289
  - About 13505CFG
    289
- Comments
  289
Section 4

377
- List of Figures
  379
- 1 Introduction
  
  381
  - Features
    381
- 2 Installation and Configuration
  
  382
- 3 LCD Interface Pin Mapping
  
  383
- 4 Cpu/Bus Interface Connector Pinouts
  
  384
- 5 Host Bus Interface Pin Mapping
  
  386
- 6 Technical Description
  
  387
  - ISA Bus Support
    387
  - Non-ISA Bus Support
    387
  - DRAM Support
    389
  - Decode Logic
    389
  - Clock Input Support
    389
  - Monochrome LCD Panel Support
    389
  - Color Passive LCD Panel Support
    389
  - Color TFT/D-TFD LCD Panel Support
    390
  - CRT Support
    390
  - Power Save Modes
    390
  - Adjustable LCD Panel Negative Power Supply
    390
  - Adjustable LCD Panel Positive Power Supply
    390
  - Cpu/Bus Interface Header Strips
    391
  - Schematic Notes
    391
- 7 Parts List
  
  392
- 8 Schematic Diagrams
  
  394
Section 5

401
- 1 Introduction
  
  405
- 2 Features
  
  406
  - S1D13505 Embedded RAMDAC LCD/CRT Controller
    406
    
    Display Buffer
    406
    
    LCD Display Support
    407
    
    Touchscreen Support
    409
    
    CRT Support
    409
    
    Jumper Selection
    409
    
    Adjustable LCD BIAS Power Supply
    409
- 3 D9000 Specifics
  
  411
  - Interface Signals
    411
    
    Connector Pinout for Channel A6 and A7
    411
    
    Memory Address (CS#, M/R#) Decoding
    415
  - FPGA Code Functionality
    415
  - Board Dimensions
    415
- 4 Parts List
  
  416
- 5 Schematic Diagrams
  
  417
- 6 Component Placement
  
  420
  - Power Consumption
    421
Table of Contents

427
- 1 Introduction
  
  431
- 2 Interfacing to the PR31500/PR31700
  
  432
- 3 S1D13505 Host Bus Interface
  
  433
  - PR31500/PR31700 Host Bus Interface Pin Mapping
    433
  - PR31500/PR31700 Host Bus Interface Signals
    434
- 4 Direct Connection to the Philips PR31500/PR31700
  
  435
  - Hardware Description
    435
  - S1D13505 Configuration
    436
  - Memory Mapping and Aliasing
    437
- 5 System Design Using the IT8368E PC Card Buffer
  
  438
  - Hardware Description
    438
  - IT8368E Configuration
    439
  - S1D13505 Configuration
    439
- 6 Software
  
  440
- 7 References
  
  441
  - Documents
    441
  - Document Sources
    441
- 8 Technical Support
  
  442
  - EPSON LCD/CRT Controllers (S1D13505)
    442
  - Philips MIPS PR31500/PR31700 Processor
    442
  - Ite It8368E
    442
Table of Contents

445
- 1 Introduction
  
  449
- 2 Interfacing to the PC Card Bus
  
  450
  - The PC Card System Bus
    450
    
    PC Card Overview
    450
    
    Memory Access Cycles
    450
- 3 S1D13505 Host Bus Interface
  
  453
  - PC Card Host Bus Interface Pin Mapping
    453
  - PC Card Host Bus Interface Signals
    454
- 4 PC Card to S1D13505 Interface
  
  455
  - Hardware Description
    455
  - S1D13505 Hardware Configuration
    457
  - Performance
    457
  - Register/Memory Mapping
    458
- 5 Software
  
  459
- 6 References
  
  460
  - Documents
    460
  - Document Sources
    460
- 7 Technical Support
  
  461
  - Epson LCD/CRT Controllers (S1D13505)
    461
  - PC Card Standard
    461
Table of Contents

465
- 1 Introduction
  
  469
- 2 Interfacing to the VR4102/VR4111
  
  470
  - The NEC VR4102/VR4111 System Bus
    470
    
    Overview
    470
    
    LCD Memory Access Cycles
    471
- 3 S1D13505 Host Bus Interface
  
  472
  - Host Bus Interface Pin Mapping
    472
  - Host Bus Interface Signals Descriptions
    473
- 4 VR4102/VR4111 to S1D13505 Interface
  
  474
  - Hardware Description
    474
  - S1D13505 Hardware Configuration
    475
- 5 Software
  
  476
- 6 References
  
  477
  - Documents
    477
  - Document Sources
    477
- 7 Technical Support
  
  478
  - EPSON LCD/CRT Controllers (S1D13505)
    478
  - NEC Electronics Inc. (VR4102/VR4111)
    478
Table of Contents

481
- 1 Introduction
  
  485
- 2 Interfacing to the MPC821
  
  486
  - The Mpc8Xx System Bus
    486
  - MPC821 Bus Overview
    486
    
    Normal (Non-Burst) Bus Transactions
    487
    
    Burst Cycles
    488
  - Memory Controller Module
    489
    
    General-Purpose Chip Select Module (GPCM)
    489
    
    User-Programmable Machine (UPM)
    490
- 3 S1D13505 Host Bus Interface
  
  491
  - Powerpc Host Bus Interface Pin Mapping
    491
  - Powerpc Host Bus Interface Signals
    492
- 4 MPC821 to S1D13505 Interface
  
  493
  - Hardware Description
    493
  - Hardware Connections
    494
  - S1D13505 Hardware Configuration
    496
  - Register/Memory Mapping
    496
  - MPC821 Chip Select Configuration
    497
  - Test Software
    498
- 5 Software
  
  499
- 6 References
  
  500
  - Documents
    500
  - Document Sources
    500
- 7 Technical Support
  
  501
  - EPSON LCD/CRT Controllers (S1D13505)
    501
  - Motorola MPC821 Processor
    501
Table of Contents

505
- 1 Introduction
  
  509
- 2 Interfacing to the TX3912
  
  510
- 3 S1D13505 Host Bus Interface
  
  511
  - TX3912 Host Bus Interface Pin Mapping
    511
  - TX3912 Host Bus Interface Signals
    512
- 4 Direct Connection to the Toshiba TX3912
  
  513
  - Hardware Description
    513
  - S1D13505 Configuration
    514
  - Memory Mapping and Aliasing
    515
- 5 System Design Using the IT8368E PC Card Buffer
  
  516
  - Hardware Description
    516
  - IT8368E Configuration
    517
  - S1D13505 Configuration
    517
- 6 Software
  
  518
- 7 References
  
  519
  - Documents
    519
  - Document Sources
    519
- 8 Technical Support
  
  520
  - EPSON LCD/CRT Controllers (S1D13505)
    520
  - Toshiba MIPS TX3912 Processor
    520
  - Ite It8368E
    520
Table of Contents

523
- 1 Introduction
  
  527
- 2 Interfacing to the NEC VR4121
  
  528
  - The NEC VR4121 System Bus
    528
    
    Overview
    528
    
    LCD Memory Access Cycles
    529
- 3 S1D13505 Host Bus Interface
  
  530
  - Host Bus Interface Pin Mapping
    530
  - Host Bus Interface Signal Descriptions
    531
- 4 VR4121 to S1D13505 Interface
  
  532
  - Hardware Description
    532
  - S1D13505 Configuration
    533
  - NEC VR4121 Configuration
    533
  - Memory Mapping and Aliasing
    534
- 5 Software
  
  535
- 6 References
  
  536
  - Documents
    536
  - Document Sources
    536
- 7 Technical Support
  
  537
  - Epson LCD/CRT Controllers (S1D13505)
    537
  - NEC Electronics Inc. (VR4121)
    537
Table of Contents

541
- 1 Introduction
  
  545
- 2 Interfacing to the NEC V832
  
  546
  - The NEC V832 System Bus
    546
    
    Overview
    546
    
    Access Cycles
    547
- 3 S1D13505 Host Bus Interface
  
  548
  - Host Bus Interface Pin Mapping
    548
  - Host Bus Interface Signal Descriptions
    549
- 4 V832 to S1D13505 Interface
  
  550
  - Hardware Description
    550
  - S1D13505 Hardware Configuration
    551
  - NEC V832 Configuration
    552
  - Memory Mapping and Aliasing
    553
- 5 Software
  
  554
- 6 References
  
  555
  - Documents
    555
  - Document Sources
    555
- 7 Technical Support
  
  556
  - Epson LCD/CRT Controllers (S1D13505)
    556
  - NEC Electronics Inc. (V832)
    556

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Epson S1D13505 Technical Manual (556 pages)

Table of Contents

Table of Contents

1 Introduction

2 Features

3 Typical System Implementation Diagrams

4 Internal Description

5 Pins

6 C. Characteristics

7 C. Characteristics

8 Registers

9 Display Buffer

10 Display Configuration

11 Look-Up Table Architecture

12 Ink/Cursor Architecture

13 Swivelview

14 Clocking

15 Power Save Modes

16 Mechanical Data

Table of Contents

1 Introduction

2 Initialization

3 Memory Models

4 Look-Up Table (LUT)

5 Advanced Techniques

6 LCD Power Sequencing and Power Save Modes

7 Hardware Cursor/Ink Layer

8 Swivelview

9 CRT Considerations

10 Identifying the S1D13505

11 Hardware Abstraction Layer (HAL)

12 Sample Code

Appendix A Supported Panel Values

Table of Contents

Section 4

1 Introduction

2 Installation and Configuration

3 LCD Interface Pin Mapping

4 Cpu/Bus Interface Connector Pinouts

5 Host Bus Interface Pin Mapping

6 Technical Description

7 Parts List

8 Schematic Diagrams

Section 5

1 Introduction

2 Features

3 D9000 Specifics

4 Parts List

5 Schematic Diagrams

6 Component Placement

Table of Contents

1 Introduction

2 Interfacing to the PR31500/PR31700

3 S1D13505 Host Bus Interface

4 Direct Connection to the Philips PR31500/PR31700

5 System Design Using the IT8368E PC Card Buffer

6 Software

7 References

8 Technical Support

Table of Contents

1 Introduction

2 Interfacing to the PC Card Bus

3 S1D13505 Host Bus Interface

4 PC Card to S1D13505 Interface

5 Software

6 References

7 Technical Support

Table of Contents

1 Introduction

2 Interfacing to the VR4102/VR4111

3 S1D13505 Host Bus Interface

4 VR4102/VR4111 to S1D13505 Interface

5 Software

6 References

7 Technical Support

Table of Contents

1 Introduction

2 Interfacing to the MPC821

3 S1D13505 Host Bus Interface