Kenwood UD-300 Service Manual page 42

UD-300
Pin functions
CIRCUIT DESCRIPTION
42
Pin No. | Pin name |1/O Function
1 | Focus OK input terminal. Used for SENS output and servo auto sequencer.
2 O | Output for changing output filter of spindle motor.
3 MON O | ON/OFF control output of spindle motor.
4 MDP O | Servo contro! of spindle motor.
5 MDS O | Servo control of spindle motor.
6 LOCK O | Outputs "H', when GFS is sampled at 460Hz and it is 'H'". Output "L", if "L" is detected eight times continuously, |
7 NC - | Not used.
8 VCOO O | Oscillation circuit output for analog EFM PLL.
9 VCO! | Oscillation circuit input for analog EFM PLL. flock = 8.6436MHz
10 TEST | | Test terminal, normally grounded.
11 PDO O | Charge pump output for analog EFM PLL.
12 Vss 1.5 GND. :
13~15 NC - | Not used.
16 VPCO © | PLL charge pump output for variable pitch.
17 VCKI 1 | Ciock input fccenter = 16.9344MHz from outside VCO for variable pitch.
18 FILO O | Filter output for master PLL (Slave = Digital PLL).
19 FILI | Filter input for master PLL.
20 PCO__| O | Charge pump output for master PLL.
21 AVss - | Analog GND.
22 CLTV |; VCO control voltage input for master.
23 AVop Analog power source (+5V). sii
24 RF | EFM signal input.
25 TEST2 | | Used for grounding.
26 TEST3 | | Used for grounding.
27 ASYO O | EFM full swing output ("L' = Vss, "H" = Voo).
28 TEST4 | | Used for grounding.
29 NC - | Not used.
30 PSSL |_| Audio data output mode changing input. Set to "'L" for serial output and '"'H" for parallel output.
31 WDCK O | D/Ainterface for 48-bit slot. Word clock f = 2 Fs
32 LRCK O | D/A interface for 48-bit slot. LR clock f = Fs
33 Voo__| - | Source voltage (+5V).
34 DA16 O | Outputs DA16 (MSB) when PSSL = 1. Outputs serial data of 48-bit slot when PSSL = 0. (2s' COMP, MSB first)
35 DA15 O | Outputs DA15 when PSSL = 1. Outputs bit clock of 48-bit slot when PSSL = 0.
36 DA14 O | Outputs DA14 when PSSL = 1. Outputs serial data of 64-bit slot when PSSL = 0. (2s' COMP, LSBfirst)
37 | DA13 O | Outputs DA13 when PSSL = 1. Outputs bit clock of 64-bit slot when PSSL = 0. |
38 DA12 O | Outputs DA12 when PSSL = 1. Outputs LR clock of 64-bit slot when PSSL = 0.
39 DA11 O | Outputs DA11 when PSSL = 1. Outputs GTOP when PSSL = 0.
40 DA10 O | Outputs DA10 when PSSL = 1. Outputs XUGF when PSSL = 0.
41 DAOQ 0 T Outputs DAO9 when PSSL = 1. Outputs XPLCK when PSSL = 0.
42 DAO8 O | Outputs DAO8 when PSSL'= 1. Outputs GFS when PSSL = 0.
43_| Oa07 | O | Outputs DAO7 when PSSL = 1. Outputs RFCK when PSSL = 0.
44 DAO6 O | Outputs DAO6 when PSSL = 1. Outputs C2PO when PSSL = 0.
45 DAO5 O | Outputs DAOS when PSSL = 1. Outputs XRAOF when PSSL = 0.
46 | DA04 | O | Outputs DA04 when PSSL = 1. Outputs MNT3 when PSSL = 0. "|
47__| DAO3 | O | Outputs DAG3 when PSSL = 1. Outputs MNT2 when PSSL = 0.
48 DAO2 O | Outputs DAO2 when PSSL = 1. Outputs MNT1 when PSSL = 0.
49 DAO1 O | Outputs DAO1 when PSSL = 1. Outputs MNTO when PSSL = 0.