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Section IV
4·93.
To clarify the functioning of the track protect
circuits, assume first that all tracks are protected. To bring
this about, diodes CR1 through CR8 are all removed from
the data card. (Refer to table 2·1.) Now, when the track
protect switch is open, the "not" TP input pin on the
command card (pin *16) faces an open input. Since resistor
MC47R2 is connected to - 2 volts, "nand" gate MC46C on
the command card is disabled. Consequently no writing can
take place.
If
the track protect switch is then closed, the
gate is enabled, writing can take place on any track, and no
track protection exists.
4·94.
Assume, now, that diodes CR1 through CR8 are
all in place on the data card. As shown in table 2·1, track
000 (octal) is then protected when switch Sl is open. The
eight diodes, together with resistor MC47R2 on the
command card, constitute a negative·logic "and" gate.
Diode CR9 constitutes a 9th input to the gate when Sl is
closed.
If
all inputs to the gate are false, the output of the
gate is false. With Sl open, the "not" TP signal is false only
when all flip·flops in the track address register are clear.
Since the register contains the track address, track 000
(octal) is protected. However, if one or more of the flip·
flops is in the set condition, "and" gate coincidence does
not exist, the "not" TP signal is true, and writing can be
conducted. This condition exists when the track address is
other than 000.
4·95.
To further illustrate the functioning of the track
protect circuits, assume that diode CR1 has been removed.
The "and" gate now has seven inputs (not counting CR9),
and the low·order flip·flop of the track address register is
not examined when determining track protect status. Track
protection exists when the T A 7 through TAl FFs are all in
the clear state; TAO can be either reset or set. This
condition occurs when the track address is 000
or 001 (octal).
4·96.
As additional diodes are removed, additional
tracks are brought into protect status when Sl is open. The
track addresses corresponding to the diodes removed are
not examined when the circuits determine protect status.
These tracks are simply given protect status at all times,
provided switch Sl is open.
4·97.
Abort Store FF. The STC instruction which
initiates a write operation resets the ABS FF on the
command card. Then, if certain fault conditions exist
during all or part of the write operation, the "not" RY
signal from the disc becomes true and the flip.flop is placed
in the set condition. The ABS FF is also set if the "not"
ACL signal from the disc becomes false; this occurs when
low line voltage is applied to the disc memory power
supply. After the completion of writing, the state of the
ABS FF can be checked by an LIA/B instruction.
If
the
flip. flop is set, bit 3 of the disc status word will be logic 1,
indicating that the write operation possibly was not
performed successfully.
4·98.
The conditions which result in setting the ABS FF
are the following:
4·12
12606B
a. Low disc speed.
b. The disc circuits which supply the "not" RY signal
are defective.
c. Disc memory not connected to the computer.
d. Disc memory not connected to the disc memory
power supply.
e. Low line voltage or no line voltage applied to the
disc memory power supply.
f.
Disc memory power supply defective
or
not turned
on.
4·99.
TERMINATION OF WRITING.
4·100.
General. Disc writing can be terminated in two
ways: by permitting all words to be transferred to the disc,
or by an abort of the write operation before its completion.
In the first method, the operation is terminated by the
DMA system without intervention by the computer
program. In the second method the operation is terminated
by a programmed abort or by an automatic abort brought
about by equipment failure.
4·101.
Termination by DMA System. When the DMA
system terminates disc writing, it issues a CLC signal to the
data card after forwarding the last word to the input
register on the card. The signal resets the Control Bit FF.
The SAC FF on the command card is cleared by the false
CB signal produced when the Control Bit FF is reset. The
Run FF is reset at the end of the current sector, when the
EOS FF on the command card is set.
If
the number of
words supplied by the DMA system is not sufficient to fill
the last sector, the last word furnished is repeated in each
word location in the track until the end of the sector is
reached. After being reset, the Run FF is not set again at
the start of the new sector, as is done when writing
continues. Therefore, the "not" W signal remains true and
the bit on the DW line is not written on the drum at the
start of the next sector.
4·102.
When the "not" W signal becomes true, the
"not" BC signal is no longer furnished by the disc, and the
bit counter and word counter cease running. These counters
are cleared at the end of the last sector written, and remain
cleared until another disc write or read operation is
initiated. Also, after the end of the last sector written, the
WRD and STR FFs remain in the set condition. Because
STR remains set, "nand" gate MC104A on the command
card does not experience coincidence, and "nand" gate
MC124B on the data card experiences continued coinci·
dence. Consequently, the Flag FF on the data card remains
reset and SRQ signals are no longer sent to the DMA
system.
4·103.
Termination by Abort. It has been noted that a
write operation can be aborted in two ways: either by a
programmed instruction or by the occurrence of certain
faults in the disc memory or disc memory power supply.
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