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12606B
and MC64E on the command card, resetting the EOS flip.
flop and ensuring that the WD5·0 flip·flops are also in the
reset condition. "Nand" gate MC34B ensures that the STR
and WRD FFs are in the set condition, and that the bit
counter is in the reset condition.
4·82.
If writing is to be continued in the next sector, the
SAC FF remains set between the two sectors. As a result,
when the second "not" SC pulse of the new sector occurs,
"nand" gate MC56B sets the Run FF. Operations then
proceed as with the previous sector, and are continued until
the operation is completed in the normal manner or
aborted. Termination proceedings are described later in this
section.
4·83.
Data Transfer to Disc. When writing takes place,
each 16·bit word in the data shift register is transferred in
serial form to the disc, low·order bit first. After the 16 data
bits have been transferred, a parity bit is furnished as the
17th bit. The track in which writing takes place is specified
by the T A 7·0 bits from the data card; these bits select the
appropriate read/write head.
4·84.
As stated earlier, when the writing of each word
takes place the disc furnishes to the command card 17
"not" BC pulses, each indicating that a bit has been written
on disc and a new bit is required. After 17 pulses have been
furnished, an additional 17 are furnished for the second
word, and so on. The pulses are provides in a continuous
train without pauses between words. However, the pulses
are not furnished between sectors. Thus 1088 pulses are
generated for every sector written (17 pulses for each of 64
words).
4·85.
At the start of every disc sector while writing,
before the first "not" BC pulse, the DW output from the
data card is sampled by the disc. This output is taken from
the reset side of FF DO. Since the WRD FF is in the set
condition during the writing of the 16 data bits, "nand"
gate MC26A on the data card is disabled, its output is true,
and "nand" gate MC26C is enabled, allowing the reset
output of FF DO to be inverted and forwarded to the disc.
4·86.
After sampling the bit on the DW line, the disc
writes the bit in the first bit position of the sector, then
starts furnishing the "not" BC pulses to the data card. The
negative·going edge of each pulse is inverted, and shifts the
word in the data shift register one position toward the
low·order end of the register. Thus, after each shift a new
bit is supplied to the DW line. This bit is written on the
disc, and another register shift takes place. The process
continues until all 16 data bits have been transferred to the
disc. Figure 4·6 shows the timing relationships.
4·87.
As each data bit is shifted out of the DO FF, the
output rank of the WP FF is toggled if the bit is a binary 1.
At the start of each word the WP FF is in the reset
condition. After 16 data bits have been transferred to the
disc, the WP FF will be in the reset state if there was an
even number of 1 's in the 16·bit word, or in the set state if
Section IV
there was an odd number of l's. Consequently, the output
of this flip·flop will be in the required state for furnishing
the parity bit. (Odd parity is used.)
4·88.
On the command card, the WRD FF is reset by the
negative·going edge of the 16th "not" BC pulse. As a result,
"nand" gate MC26A on the data card is enabled, and the
parity bit in the WP FF is forwarded to "and" gate MC26C.
At this time, the DO FF contains a binary 0, and its reset
output serves as an enable for MC26A. (The binary 0 in DO
was shifted down the register from FF D16, which was
reset before shifting started.) MC26C inverts the parity bit
to the required form, and forwards the bit to the disc.
4·89.
While the parity bit is being sent to the disc, a new
word is gated into the data shift register from the input
register. Then, when the negative·going edge of the 17th
"not" BC pulse indicates that the parity bit has been
written, the WRD FF is set. As a result, "and" gate MC26C
on the data card is again ready to forward data from FF DO
to the disc. The write operation continues without inter·
ruption, with the first bit of the new word being recorded
on the disc immediately after the parity bit of the
preceding word.
4·90.
Words continue to be transferred to the disc until
the end of the first sector is reached.
If
additional sectors
are to be written, the procedure described is repeated for
each sector. The Run FF is set and reset, respectively, at
the beginning and end of each sector. However, the SAC FF
remains set until the operation is completed or aborted.
4·91.
Incomplete Sector. If the number of words to be
written is not a multiple of 64, the last sector will not be
completely filled. When an operation of this type takes
place, the DMA system supplies the data card with a CLC
signal after it has furnished the last word. This signal resets
the Control Bit FF, which in turn resets the SAC FF.
However, the Run FF remains set until the end of the
sector. As a result, the "not" W signal remains false and
writing continues. However, the data card no longer
receives SCM, SCL, IOGE(B), or 100 signals from DMA.
Therefore, the contents of the input register remain
unchanged. These contents will be the last word written on
the disc. Each word·time for the remainder of the last
sector, the contents of the input register will be gated into
the data shift register and transferred to the disc as the
word to be written. Thus, the last word will be repeated on
the disc until the end of the sector is reached. The Run FF
is then reset, the "not" W signal becomes true, and the
operation ceases. Until the Run FF is reset at the end of the
sector, bit 0 of the disc status word is logic 1. (As noted
earlier, if either the Control Bit FF or the Run FF is set,
bit 0 of the status word is logic 1.)
4·92.
Track Protection. When track protect switch Sl
on the data card is closed (in the down position), no tracks
are protected against writing. In this nonprotect situation
the "not" TP signal is true, and "nand" gate MC46C on the
command card is enabled. If the track protect switch is
open, the "not" TP signal is false if the track address
register contains an address for a protected track.
4·11
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