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INSTRUCTION SUMMARY
Load
Store
Arithmetic
Logical
Branch
Register Transfer
Single and double word
Single and double word
18 bit parallel addition
AND, OR and EXCLUSIVE OR
Conditional and unconditional
To subroutine
BUFFER SELECTOR BUFFER UNITS
Bit Buffer Unit
10 simplex channels input and 10 simplex channels output/ module
10 half-duplex channels/module
10 full-duplex (or echoplex) channels/module
Module data .rates (bits/ sec)
45
50
56.25
75
110
150
Code level: 5, 6, 7, or 8 bits/character
Character format: start/ stop bit asychronous;
one stop bit (minimum).
Compatible digital subsets: 103A; 103B.
20 ma d-c loop or bipolar voltage interface.
Character Buffer Unit
2 simplex channels/ module
2 half-duplex channels/module
1 full-duplex channel/module
Time in Microseconds
14 and 21
*
14 and 21
14
14
7
21
7
*
For ease of computation the 6. 94 u sec memory cycle is rounded to 7. 0 u sec.
B-2
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