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22 HW Processor (HWP) and Sound Output (SDAC2)
Bits 10–0 RESAMPRATE[10:0]
These bits set the audio sampling frequency of the SDAC2.
The audio sampling frequency is calculated as follows:
Sampling frequency = f
where
f
SDAC2CLK
RESAMPRATE: Value set in the SDAC2RESAMP.RESAMPRATE[10:0] bits
Note: This register is used by the HWP. Do not write any data to this register while the HWP operation
is enabled (HWPCTL.HWPEN bit = 1).
SDAC2 Tone Divider Register
Register name
Bit
SDAC2TONE
15–0 TONEDIV[15:0]
Bits 15–0 TONEDIV[15:0]
These bits set the frequency of the square-wave tone frequency when the SDAC2CTL.TONEON bit =
1 (square-wave tone generator enabled).
The tone frequency is calculated as follows:
Tone frequency = f
where
f
SDAC2CLK
TONEDIV: Value set in the SDAC2TONE.TONEDIV[15:0] bits
22-32
× (1,024 / RESAMPRATE)
SDAC2CLK
:
SDAC2 operating clock frequency set using the SDAC2CLK register [Hz]
Bit name
Initial
0x4000
/ [(4 × TONEDIV + 4) × 2]
SDAC2CLK
: SDAC2 operating clock frequency set using the SDAC2CLK register [Hz]
Seiko Epson Corporation
Reset
R/W
H0
R/W
–
S1C31D41 TECHNICAL MANUAL
(Eq. 22.1)
Remarks
(Eq. 22.2)
(Rev. 1.1)
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