Timers
15.2.2.9 Timer 1 Interrupt Control Register
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
15-20
Table 15-20. INT_CTRL Register
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
0
0
0
0
0
R
R
R
R
R
Table 15-21. INT_CTRL Register Definitions
BITS FIELD NAME
31:5
///
Reserved Read as zero.
Timer 1 Interrupt Enable During Capture 1 Operation
4
CAP1_EN
0 = No interrupt request occurs for Capture 1.
1 = Interrupt request occurs for Capture 1.
Timer 1 Interrupt Enable During Capture 0 Operation
3
CAP0_EN
0 = No interrupt request occurs for Capture 0.
1 = Interrupt request occurs for Capture 0.
Timer 1 Interrupt Enable Upon Compare 1
2
CMP1_EN
0 = No interrupt request occurs for Compare 1.
1 = Interrupt request occurs for Compare 1.
Timer 1 Interrupt Enable Upon Compare 0
1
CMP0_EN
0 = No interrupt request occurs for Compare 0.
1 = Interrupt request occurs for Compare 0.
Timer 1 Interrupt Overflow Enable
0
OVF_EN
0 = No interrupt request occurs when counter overflows.
1 = Interrupt request occurs when counter overflows.
LH75400/01/10/11 (Preliminary) User's Guide
26
25
24
23
22
///
0
0
0
0
R
R
R
R
R
10
9
8
7
///
0
0
0
0
R
R
R
R
R
0xFFFC4000 + 0x34
DESCRIPTION
6/17/03
21
20
19
18
0
0
0
0
0
R
R
R
R
6
5
4
3
2
0
0
0
0
0
R
RW
RW
RW
17
16
0
0
R
R
1
0
0
0
RW
RW