Sharp DV-500D Technical Manual page 114

Pin No. Terminal name I/O
25 ED0
26 ED1
27 ED2
28 ED3
29 ED4
30 ED5
31 ED6
32 ED7
33 TEST
34 PDON
35 PDOP
36 RLLD
37 LPFN
38 LPFO
39 VCOF
40 SLCO
41 AVSS
42 AVR
43 VRC
44 PVR
45 AVDD
46 RVR2
47 RVDD
48 RFIN
49 RVSS
50 RVR1
51 DVR
52 DMO
53 RASN
54 CASN
55 MOEN
56 MWEN
57 DVSS
58 DVDD3
59 MA9
60 MA8
61 MA7
62 MA6
63 MA5
64 MA4
65 MA3
66 MA2
67 MA1
68 MA0
69 DVSS
70 DVDD5
71 MD7
– User use is prohibited (N.C.) since it is for shipping adjustment. Open
–
–
–
–
–
–
–
I For shipping adjustment.
O PLL phase error signal output. (Negative polarity)
O PLL phase error signal output. (Positive polarity)
O RLL detection result output.
I PLL loop filter amp. reverse input.
O PLL loop filter amp. output.
O VCO filter terminal.
O Built-in comparator reference voltage output terminal.
– Analog power. (0V)
O Non-PLL system analog reference potential. (1.65V)
– Resistance division point potential. (For analog reference
potential generation: 1.65)
O PLL system analog reference potential. (1.65V)
– Analog power. (3.3V)
– 2nd reference voltage. (For capacitor connection)
– Exclusive-use power terminal. (3.3V)
I RF signal input.
– Exclusive-use power terminal. (0V)
– 1nd reference voltage. (For capacitor connection)
I DMO reference potential. (1.65V recommended)
O Disc equalizer output for DVD. (Triple value PWM + HiZ)
O External RAM row address selection. (Negative logic)
O External RAM row address selection. (Negative logic)
O External RAM output permission signal.
O External RAM read/write selection.
– Digital power. (0V)
– Digital power. (3.3V)
O External RAM address bus.
O External RAM address bus.
O External RAM address bus.
O External RAM address bus.
O External RAM address bus.
O External RAM address bus.
O External RAM address bus.
O External RAM address bus.
O External RAM address bus.
O External RAM address bus.
– Digital power. (0V)
– Digital power. (5V)
I/O External RAM data bus.
Operation function
12-21
DV-560H
Remarks
Set to "L"
For logic cell
For logic cell
For I/O cell
For I/O cell
TTL level